UART_Verilog

这是一个LCD1602底层驱动代码，TI公司LM3S系列的(This is a LCD1602 underlying driver code, TI company LM3S series)

说明：  用Verilog实现的基于FPGA的简单避障游戏(A game based on FPGA,using Verilog)

AL422B,FPGA写的控制时序。XIWANGDUIDAJIAYOUYONG(AL422B,timing of AL422b.)

Design FPGA in Labview

说明：  risc 8 by coonan compatible with PIC16C57

基于FPGA的DPSK调制，包括matlab仿真代码，NCO载波发生器，绝相变化，上变频等，基于Altera FPGA实现，并通过仿真验证。

可实现两个4bit补码的加法及减法，有溢出提示(adder with overflow hint)

用Verilog实现一个基于Mesh拓扑结构的路由器网络(Using Verilog to implement a router network based on Mesh topology)

本源码为Nios II的开发示例,主要演示基于Nios II的uCOS的移植。开发环境QuartusII。 本示例十分经典，对基于SOPC开发的FPGA初学者有很大帮助。(The source code for the Nios II development of examples, mainly based on the Nios II shows the uCOS transplant. Development environment QuartusII. This example is very classic, FPGA-based SOPC development of great help for beginners.)

使用Verilog语言编程，在Quartus ii 上实现的误码检测装置，并通过单片机将误码结果显示在LCD上。本代码具有一定的工程实践价值。(Using the Verilog language programming, implemented on the Quartus ii error detection device, and the result of errors by the microcontroller on the LCD display. The code has some value engineering practice.)