EDA常用计数函数VHDL程序设计，减法计数器：可预置数：

说明：  CAN VHDL Code. Behavioral implementation of CAN bus interface.

说明：  学习使用quartus modelsim(learn to uee quartus modelsim)

本实验为UART回环实例，实验程序分为顶层unrt_top、发送模块uart_tx、接收模块 uart_rx，以及时钟产生模块clk＿div。uart＿rx将收到的包解析出8位的数据，再传送给 uart_tx发出，形成回环。参考时钟频率为100MHz，波特率设定为9600bps。(This experiment is an example of UART loop. The experimental program is divided into top-level unrt_top, sending module uart_tx, receiving module uart_rx, and clock generation module clk_div. Uart_rx parses the received packet into 8 bits of data and sends it to uart_tx to send out, forming a loop. The reference clock frequency is 100 MHz and the baud rate is set to 9600 bps. stay)

EP2C5核心电路原理图，包括protel文件及其相应封装库-EP2C5 Core circuit Sch

fpga驱动TLC7528程序，相当好用，绝对能用(FPGA PROGRAM OF TLC7528)

应用背景电子自动售货机使用FPGA。 ；使用简单的Verilog仿真，我们可以很容易地实现硬件设计在我们的现实生活环境满足效率问题，成本和透明度。通过使用基于FPGA的EVM关键技术电子自动售货机使用FPGA

用PrimeTime的技巧，解决复杂时钟问题。(The world of telecommunications chips is full of messy clocking situations. This paper will cover the tricks and tehniques that author Paul Zimmer has developed to avoid the need to pour over reams of timing reports looking for problems. Best paper winner at SNUG San Jose 2001!)

verilog 硬件编程实现bpsk调制(verilog hardware, programming bpsk Modulation)

正弦波在dspbuilder下产生VHDL源码及其测试激励文件的matlab模型,在modelsim下仿真通过-sine wave in dspbuilder under VHDL source code and test incentives document matl ab model, the simulation under through modelsim

The description header can be found in signal_processing_library.h.