EDA常用计数函数VHDL程序设计，减法计数器：可预置数：

收集了目前关于FPGA设计的论坛，大家如果有什么疑问，可以到这些论坛上求助。-The collection of the current design of the forum on the FPGA, there is little doubt if the U.S. can go to for help on these forums.

本文档对quartus与modelsim运用操作描述十分详细，对初学者，会有很大帮助！(Quartus and modelsim this document on the use of operations described in great detail, for beginners, there will be a great help!)

verilog i2c master rtl+testbench 转自特权同学(verilog i2c master rtl+testbench)

08EE06EDA 实验 4（VHDL 状态机设计_序列检测器）6/7/2008-design thesis requirement by vhdl

cordic算法，实现加减乘除、幂次方、开方的运算(CORDIC algorithm implementation, power add, subtract, multiply and divide and square root operations)

controller for sending serial data at different speeds

应用背景通用模块，以产生可重构的源时钟频率的传输速率。该模块可用于UART，自定义串口协议等。提供一个时钟发生器模块产生可选 ；-波特利率和；——时钟源（可选择分因素） ；还产生接收 ；——时钟的16倍，8倍，倍，倍的传输波特率 ；关键技术UART，VHDL，FPGA，CPLD programmanle逻辑器件。设备无关的代码

VHDL2verilog的程序，相信对大家很有帮助-VHDL2verilog procedures, I believe very helpful to everyone

verilog入门基础以及简单编程介绍，verilog是近几年发展迅速的一门硬件语言-Verilog entry basis, as well as introduce a simple programming, verilog in recent years the rapid development of a hardware language

VGA 测试程序，可显示彩色条纹，用vhdl语言编写，经过测试，运行稳定，带有注释！-VGA test procedure can be displayed color stripes, using VHDL language, tested and stable operation with Notes!