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AD7991_7995_7999
AD7991_7995_7999转换器说明(4-Channel, 12-/10-/8-Bit ADC with
I2C-Compatible Interface in 8-Lead SOT-23)
- 2013-05-15 20:14:11下载
- 积分:1
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float_int
自己编写的,浮点数与整数之间的转换的Verilog HDL实现(Written by myself, it is converted into Verilog HDL integer floating point implementation)
- 2020-12-18 10:29:11下载
- 积分:1
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Digital Cymometer VHDL procedures and simulation of the file name: plj.vhd.
数字频率计VHDL程序与仿真
文件名:plj.vhd。
--功能:频率计。具有4位显示,能自动根据7位十进制计数的结果,自动选择有效数据的
--高4位进行动态显示。小数点表示是千位,即KHz。
-Digital Cymometer VHDL procedures and simulation of the file name: plj.vhd.- Function: frequency meter. With four shows that will automatically count seven decimal results, automatic selection of effective data- four for the high dynamic display. Decimal point that is 1000, or KHz.
- 2022-08-04 07:22:59下载
- 积分:1
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一个用VHDL语言编写的双端口存储器程序,可下载在FPGA中使用
一个用VHDL语言编写的双端口存储器程序,可下载在FPGA中使用-Written in VHDL language using a dual-port memory program can be downloaded in the FPGA using
- 2023-06-18 05:20:03下载
- 积分:1
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网卡的IP核,下载即可用,解压到指定目录下就可以了,参照里面的read me.
网卡的IP核,下载即可用,解压到指定目录下就可以了,参照里面的read me.-NIC
- 2022-03-01 02:33:22下载
- 积分:1
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CPLD
控制三相步进电机及光电编码器的采集,当电机停止时,保证三相里面只有一相相通,防止停止时电流过大.(Control three-phase stepper motor and optical encoder collection, when the motor stops to ensure that only one phase of three-phase inside the heart, and to prevent too much current is stopped.)
- 2008-05-26 11:37:38下载
- 积分:1
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SDH接收处理
模拟SDH帧结构,设计了状态机,能从连续传输的SDH字节流中找出帧头;从SDH字节流中,提取E2字节,并按照64K速率分别串行输出E2码流及时钟;设计了输入信号,输出包括E2串行数据、E2串行时钟和SDH帧头位置指示
- 2023-07-26 18:40:02下载
- 积分:1
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SinGen
使用Verilog编写的正弦波生成工程,使用ROM核产生,利用mif文件(Written using Verilog sine wave generation projects using ROM nuclear generation, use mif file)
- 2015-04-24 16:40:21下载
- 积分:1
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IIR-digital-filter-
采用双线性变换法设计IIR数字滤波器设计的c代码,包括低通、高通和带通(Document recording the design of IIR digital filter c code)
- 2011-09-05 17:47:58下载
- 积分:1
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altera_fft
verilog实际例子,非常适合初学者学习(verilog practical examples, very suitable for beginners to learn)
- 2020-12-06 16:49:22下载
- 积分:1