EDA常用计数函数VHDL程序设计，减法计数器：可预置数：

verilog实践 elc_clock 电子时钟设计(Verilog design practice elc_clock electronic clock)

这是通过使用 VHDL 代码的 FFT 库函数。它可以切换的 FFT 16 点和 64 点之间的长度。它包含蝴蝶、捻因子、 ROM、 RAM 和等等。它可以成功运行在 Quartus 2 或其他软件上。

一个8X8的矩阵键盘的VHDL文件,并且有长安键和短按键之分,即一共能做到128个键值,扫描用的时钟用1ms的就行了-A 8x8 matrix keyboard VHDL files and have Changan and short keys of key points, namely, to achieve a total of 128 keys, scanning with the clock used on the list of 1ms

matlab file for image contrast..

吠陀复用代码执行乘法的4位和8位使用进位选择加法器

自己今年的毕业设计DDS波形发生器,有正弦波,方波,三角波,锯齿波.-Their own design this year

512×8bid的FIFO 含工程文件，基于QUARTUs-512 × 8bid the FIFO with the project document, based on the QUARTUsII

We present elliptic curve cryptography (ECC) coprocessor, which is dual-field processor with projective coordinator. We have implemented architecture for scalar multiplication, which is key operation in elliptic curve cryptography. Our coprocessor can be adapted both prime field and binary field, also contains a control unit with 256 bit serial and parallel operations , which provide integrated highthroughput with low power consumptions. Our scalar multiplier architecture operation is perform base on clock rate and produce better performance in term of time and area compared to similar works. We used Verilog for programming and synthesized using Xilinx Vertex II Pro devices. Simulation was done with Modelsim XE 6.1e, VLSI simulation software from Mentor Graphics Corporation especially for Xilinx devices.

自己收集的VHDL例程代码，适合初学者学习用，希望能给大家带来帮助。-Collected their own routines VHDL code, suitable for beginners to learn, I hope we can help.

说明：  基于FPGA和弦！！！音乐芯片的设计与实现！！！(Design and implementation of FPGA chip based on the chord music)