EDA常用计数函数VHDL程序设计，减法计数器：可预置数：

计算燃料电池膜的传质分析，包括各层之间的氧气、二氧化碳以及水的传质。(Calculating cell mass transfer)

直接数字频率合成器（Direct Digital Frequency Synthesizer：DDFS）的VHDL程序,开发环境是QuartusII,系统时钟为50MHz，由PLL产生DDFS的工作时钟166.67MHz,地址位宽为24位，频率字为20，相位字为10，RAM用于存储查找表，其地址位宽为10，数据位宽为8。-Direct Digital Frequency Synthesizer ( DDFS) of the VHDL program, the development environment is QuartusII, the system clock to 50MHz, the work of DDFS generated by PLL clock 166.67MHz, address bit-width of 24-bit frequency word is 20, phase word for 10, RAM used to store look-up table, its address is 10 bits wide, the data is 8 bits wide.

LDPC码校验节点（checknode）进行奇偶校验方程时的vhdl编程，硬件语言实现-LDPC check nodes (checknode) carried out at the time of parity equation VHDL programming, hardware language

Introduction to learn laboratry with altera quartus II 9.1

16位浮点FFT算法的VHDL实现有测试文件！-16-bit floating-point FFT algorithm VHDL realization of a test file!

针对串行存储器M25P80应用的verilog程序-M25P80 serial memory for applications Verilog program

FPGA中按键弹跳消除模块的研究与应用，原理和例子都非常好-FPGA to eliminate bounce in key research and application modules, principles and examples are very good

LDPC码的FPGA实现，大家相互学习下。。(the code of LDPC implementation by FPGA)

sdram控制器的开发程序，还有文档，可以参考以下(SDRAM controller development process, there is a document, you can refer to the following)

说明：  quartus II中文用户教程(英文版的完全翻译）,和一切爱好可编程器件的同仁共勉之(Quartus II Chinese user guide (English version of the full translation) love and all programmable devices colleagues share Zhi)