EDA常用计数函数VHDL程序设计，减法计数器：可预置数：

verilog编写的ds18b20温度传感器程序，可综合(ds18b20 program written in verilog)

VHDL BASED DATA COMPRESSION

D-flip flop vhdl implement code

可在FPGA上运行的8051 IP coore，是学习FPGA及SPOC的好资料。 (8051 IP coore, can be run on the FPGA is good information to learn FPGA and SPOC.)

IT IS THE DP MEMORY MODULE. IT CONTROLS THE DP MEMORY

verilog仿真硬件的工具qiartus2的使用教程,内容简单易懂,初学必备(Verilog simulation tool for hardware qiartus2 the use of tutorials, easy-to-read content, learning essential)

HARIS角点检测Harris角点检测HARRIS CORENR探测器

MTK平台硬件培训MTK平台硬件培训MTK平台 GSM双频手机接收信号 处理流程MTK平台 GSM双频手机接收信号 处理流程 (MTK platform hardware training platform hardware training MTK MTK GSM dual-band mobile phone platform to receive the signal processing)

先设计序列发生器产生序列：1011010001101010；再设计序列检测器，检测序列发生器产生序列，若检测到信号与预置待测信号相同，则输出“1”，否则输出“0”，并且将检测到的信号的显示出来。(First design sequence generator sequence: 1011010001101010 redesign sequence detector to detect sequence generator sequence, if the same signal is detected with the preset test signal output " 1" , otherwise " 0" , and the detection display signal out.)

io 组件，用vhdl实现io端口的控制，包括输入输出，握手信号，-io port VHDL code