登录
首页 » Verilog » Gaussian Random number generator (hardware implemented)

Gaussian Random number generator (hardware implemented)

于 2022-03-25 发布 文件大小:1.97 MB
0 230
下载积分: 2 下载次数: 1

代码说明:

This is hardware implemented Gaussian random number generator based on the article attached in the folder "Document" The system is based on the Ziggurat Gaussin random algorithm and implemented when I was under-graduate. Although it is not my original system, it is so helpful cause I can acquire a lot of useful skills of verilog programming such as pipeline. It is well simulated on the synthesis tool (ISE14.7) and the printed data can be verified using Matlab which is in the "Document" folder. The testbench fils is tb_Zigg.v, and the top module file is top_Zigg.v Goodlucks~

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • 移位寄存器(右移和左移)
    module shiftrne(R,L,E,w,Clock,Q);   parameter n=4;   input [n-1:0]R;   input L,E,w,Clock;   output reg [n-1:0]Q;   integer k;      always@(posedge Clock)   begin     if(L)         Q
    2023-08-01 00:40:03下载
    积分:1
  • S6_VGA
    1。源文件保存在src目录,QII的工程文件保存在Proj目录; 2。程序实现的功能是在VGA显示器上显示彩色条纹,共8种颜色, 可以使用嵌入式逻辑分析仪观测信号; 3。modelsim仿真文件在proj--simulation--modelsim中(1. The source file is saved in the src directory QII project file is saved in the directory Proj 2. The functionality of the program is displayed on a VGA monitor color stripes, 8 colors, you can use the embedded logic analyzer observed signals 3. the modelsim simulation files in the proj- simulation- modelsim)
    2012-11-04 18:26:48下载
    积分:1
  • BCD 2 格雷码转换器
    符号化的表达数据 / 信息称为代码。基地或二进制数的基数是 2。因此,它有两个独立的符号。使用的符号是 0 和 1。一个二进制数字称为作为一位。一个二进制数由序列组成的位,每个 0 或 1。每一位分量的基于二进制点及其位置。每个位位置的重量是一个 2 的幂,大于其立即右侧位置的重量。e.g.二进制数是 100011 相当于十进制数 35。
    2022-01-25 23:47:03下载
    积分:1
  • fft_ex1
    基于verilog的FFT设计,使用vivado作为开发平台(Verilog based on the FFT design, the use of vivado as a development platform)
    2021-02-24 23:39:39下载
    积分:1
  • FPGA驱动DM9000
    通过FPGA驱动DM9000的程序源代码,可以实现UDP协议传输,长时间测试速率不掉,可以参考
    2022-09-23 16:40:04下载
    积分:1
  • shift_reg
    Shift reg in vhdl, a first example to start
    2011-03-27 10:35:25下载
    积分:1
  • 100powertips
    these are the source codes for the book " 100 power tips for FPGA designers"
    2012-08-20 14:59:29下载
    积分:1
  • VGA图像
    此代码显示图像(BMP)进行监控。该代码有C编程(bmp图像==> COE文件)所以,我们使用的核心发生器添加COE文件。这是800x600的分辨率和扩大的形象。如果你想要原始图像,改变memaddr一部分。
    2022-02-16 00:13:54下载
    积分:1
  • ddr3_test
    说明:  通过循环读写DDR3内存,了解其工作原理和DDR3控制器的写法,由于DDR3控制复杂,控制器的编写难度高,这里笔者介绍XILINX的MIG控制器情况下应用,是后续音频、视频等需要用到SDRAM实验的基础。(Through reading and writing DDR3 memory circularly, we can understand its working principle and the writing method of DDR3 controller. Because of the complexity of DDR3 control, it is difficult to write the controller. Here, the author introduces the application of Xilinx's MIG controller, which is the basis of SDRAM experiment for subsequent audio and video.)
    2021-04-16 10:00:15下载
    积分:1
  • main
    完整的GMSK调制及维特比译码,程序中包括了高斯滤波器的设计,调制相位的计算,并采用了维特比译码算法解调出原始码元,最后计算了其误码率。(Complete GMSK modulation and Viterbi decoding, the program includes a Gaussian filter design, the calculation of the phase modulation, and uses the Viterbi algorithm demodulates the source element, the final calculation of the bit error rate.)
    2020-11-03 16:19:54下载
    积分:1
  • 696516资源总数
  • 106914会员总数
  • 0今日下载