VHDL2verilog的程序，相信对大家很有帮助

用VHDL语言来实现一个电子时钟，可以调时间。小时，分，秒。可以下载到实验箱来运行验证。-use VHDL to achieve an electronic clock, the time can be set aside. Hours, minutes and seconds. Experiments can be downloaded to the box to run test.

FPGA将从CY7C68013读到的数写入SRAM-FPGA will read a few CY7C68013 write SRAM

WM8731芯片的音效处理verilog代码， WM8731芯片是音频ADCDAC芯片(WM8731 audio processing chip verilog code, WM8731 chip audio ADC DAC chip)

vhdl code for fir filter

这是用 vhdl 语言编码的可重构的 fir 滤波器设计 fir 滤波器的实现代码

VHDL数字系统设计工程实践，包含实验的原理，真值表和结构图描述，以及相关的VHDL代码。-VHDL digital system design engineering practice, including the principle of the experiment, truth table and chart descriptions, and associated VHDL code.

（1）距离算法研究和设计； （2）采用FPGA/CPLD实现。 -(1) distance algorithm and design (2) using FPGA/CPLD implementation.

一种基于LUT的预失真方法。其中的一部分，有参考价值。-one method of DPD based on LUT

QAM调制，基于FPGA的实现，包含有乘法器模块、升降余弦滤波器模块、QAM序列生成模块(QAM modulator,the implementation based on FPGA,include MUL、FIRCOS and QAM generate)

说明：  实现24小时计时，因为位数不够，这里是12进位，可自行调整进位数(Realize 24-hour timing, because the number of digits is not enough, here is 12 carry, you can adjust the carry number by yourself.)