De2 lcd1602显示器控制

QFSK的调制与解调，用C写的主程序，汇编写的调制与解调的子程序(QFSK the modulation and demodulation, with the main program in C, compile writing, the modulation and demodulation of the Subprogram)

CMV2000采集的数据，进行图像的位对齐，图像的预处理

利用matlab设计了一个切比雪夫滤波器，并且对滤波器性能进行了仿真分析。(Using the matlab design a chebyshev filter, and has carried on the simulation analysis on filter performance. )

E1 deframmer and Frammer.

本程序为四路抢答器verlog HDL语言工程实例。(This program is four Responder verlog HDL language engineering examples.)

实现基于NIOS的 EP3C16与加速度传感器NMA7455的IIC基本通信(Realization of based on NIOS EP3C16 and acceleration sensor NMA7455 IIC of basic communication )

FPGA实现串口发送 Verilog 语言(Serial reception FPGA Verilog language.)

adder 18b trong chuong trinh verilog

本文针对如今我国视频监控的需要，设计并完成了一种基于FPGA芯片的视频监控系统。该系统使用Verilog HDL语言描述整个硬件架构，使得系统性能更为稳定，操作更为简单。该系统通过OV7670摄像头获取图像数据从CMOS图像传感器引入FPGA，并编写了总线接口以便将数据交给Nios Ⅱ处理器处理。经过FPGA采集、

利用VHDL语言描述出一个双脉冲，可任意设置两脉冲长和中间时间间隔。(A double pulse is described in VHDL language, and the two pulse length and the intermediate time interval can be arbitrarily set.)