fifo

基本功能的cpu，自定义内存内容~了解CPU运作原理~(design of cpu,VHDL environment~)

16位进位加法器保存，它的Verilog代码，使用XILINX的描述和仿真，Modelsim的

这是 ；一种缓存设计的Verilog代码，使用先进先出算法。大约2000行代码，该程序包含缓存替换算法的实现。图像规则的选择，以及所有的模拟。这个设计有很多模块。此模块包含替换执行和测试平台

基于FPGA的波束形成，包括ad转换，数据存储等部分。。(FPGA-based beamforming, including ad conversion, data storage and other parts. .)

数字通信系统相移键控CPSK信号和差分相移键控的调制与解调的VHDL代码(Phase shift keying digital communication system CPSK signals and differential phase-shift keying modulation and demodulation of the VHDL code for)

基于Basy3的贪吃蛇小游戏，实现了相关功能。(Snake Eating Game Based on Basy3)

说明：  希望对VHDL的学习大家有帮助，望大家指出错误，浮想交流！(We want to learn VHDL help, hope you point out an error, daydreams exchange!)

资源描述 利用实验板实现模六十计数，即00—01—02—03—04—…59—00—01…，并在Basys2实验板的AN1~AN0或（LD7~LD0）上显示。 下载配置文件到实验板BASYS2上，观察验证实验现象。  使用verilog语言设计实现---模六十计数器

资源描述应用背景应用背景ARM设计的开源总线协议 ；呼吁对芯片的标准系统的AMBA总线，I2C也是类似的芯片 ；标准，使这两个协议之间的通信标准的I2C的新娘可以用APB。这个代码是有帮助的，希望了解这座桥的基本工作原理。

This is hardware implemented Gaussian random number generator based on the article attached in the folder "Document" The system is based on the Ziggurat Gaussin random algorithm and implemented when I was under-graduate. Although it is not my original system, it is so helpful cause I can acquire a lot of useful skills of verilog programming such as pipeline. It is well simulated on the synthesis tool (ISE14.7) and the printed data can be verified using Matlab which is in the "Document" folder. The testbench fils is tb_Zigg.v, and the top module file is top_Zigg.v Goodlucks~