CRC _ Verilog 16

本示例为基于FPGA红色飓风一代IDS-EP1C6/12开发板的USB传输，实现了pc端接收来自FPGA开发板的数据，并显示条纹，具体使用说明见解压后的说明文档。(This example is based on red hurricane generation FPGA development board' s USB transfer IDS-EP1C6/12 realized pc client receives the data from the FPGA development board and display stripes, detailed instructions, see the documentation after decompression.)

说明：  实现对LCD1602的Verilog HDL编程(the program for LCD1602 based on Verilog HDL)

基于matlab的BOC仿真程序，包含BOSK调制等。(Based on the matlab the BOC simulation program, contains modulation BOSK.)

CAN总线的数据采集，FPGA到USB。verilog hdl语言。(CAN bus data acquisition, FPGA to the USB. verilog hdl language.)

说明：  用VERILOG语言实现的频谱分析仪（FFT)(VERILOG language with the Spectrum Analyzer (FFT))

FPGA通过AXI总线传输数据给ARM,ARM使用DMA方式接收数据！(FPGA to ARM Bridge design example)

E1 deframmer and Frammer.

VHDL写时钟，分频模块什么，实现计时。定点报时，定点闹钟，显示年月日。(verilog HDL)

可以获取各种字符，并在数码管显示出来，非常的靠谱且稳定(Various characters can be acquired and displayed on the digital tube.)

thesis about design and implementation neural network using FPGA