-
gundong
说明: 通过按键输入学号,并循环显示:
电路功能描述:通过Ego1上的按键输入自己的学号(8位10进制数),并存储在32位的寄存器中;8位10进制数输入完成后,实现滚动显示效果。(Enter the student number by pressing the key, and display it in a cycle:
Circuit function description: input one's own student number (8-digit decimal number) through the key on ego1, and store it in 32-bit register; after the completion of 8-digit decimal number input, the scrolling display effect is realized.)
- 2020-12-19 16:09:10下载
- 积分:1
-
Manip_NIOS_1
nios processor example 1
- 2015-05-22 00:17:43下载
- 积分:1
-
huawei
华为内部资料,包括verilog电路设计,硬件工程师手册,verilog约束,synplify使用指南等。内容较全面。(Huawei internal information, including verilog circuit design, hardware engineers manual, verilog constraints, synplify use guides. Content more comprehensive.)
- 2015-07-11 20:08:52下载
- 积分:1
-
MifFileGen
VC++6.0软件生成Altera公司FPGA内部存储器ROM初始化数据mif格式文件。方便通过QuartusII导入波形等参数。强调这个是例子,生成的是一个定点的正弦数据表文件,需要用到的请自行修改源代码。(This software generates internal memory ROM initialization mif format data file for FPGA product by Altera. Facilitate the passage of the waveform parameters such as import QuartusII)
- 2013-07-19 02:32:45下载
- 积分:1
-
SD-Host-Controller-master
说明: sd卡的verilog代码,包含一些sd卡例程(SD card Verilog code, including some SD card routines)
- 2021-04-29 13:48:42下载
- 积分:1
-
costas_BPSK
说明: 文档科斯塔斯环路滤波器。。。。。般若撒根本(wendangsafwrfgvearbeabf)
- 2019-10-29 20:06:34下载
- 积分:1
-
Verilog 按键消抖程序
使用Verilog HDL 语言在cyclone IV 上实现功能按键控制灯,主要目的是实现按键的消抖程序,加深理解Verilog HDL 语言的并行执行方式
- 2022-01-28 07:30:28下载
- 积分:1
-
multiplier.tar
用vhdl实现的booth算法乘法器,包含了multiplexer和rca adder,同时提供了一个测试文件,modelsim测试通过(Algorithm with a booth multiplier vhdl implementation, including a multiplexer and rca adder, while providing a test file, modelsim test pass)
- 2021-04-14 13:18:55下载
- 积分:1
-
Gaussian Random number generator (hardware implemented)
This is hardware implemented Gaussian random number generator based on the article attached in the folder "Document"
The system is based on the Ziggurat Gaussin random algorithm and implemented when I was under-graduate.
Although it is not my original system, it is so helpful cause I can acquire a lot of useful skills of verilog programming such as pipeline.
It is well simulated on the synthesis tool (ISE14.7) and the printed data can be verified using Matlab which is in the "Document" folder.
The testbench fils is tb_Zigg.v, and the top module file is top_Zigg.v
Goodlucks~
- 2022-03-25 01:29:44下载
- 积分:1
-
代码可以实现时隙交换MT89L80芯片功能,完成256x256个时隙交换
使用Verilog编写代码,实现集成芯片MT89L80的功能,代码配置ram后可以直接使用,完成256x256个时隙交换,其中主要模块包括接收模块、发送模块、cpu接口模块,寄存器配置模块,接续寄存器模块等。
- 2022-09-12 20:55:03下载
- 积分:1