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iic master

于 2022-12-31 发布 文件大小:8.00 kB
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iic master 通过FPGA验证··成功对eeprom读写操作 clk_div:FPGA 板子分频时钟,满足SCL时钟线速度达400KB main_state.v:顶层状态机,控制master接口整个工作过程 scl_generator.v:master接口,有SCL状态机产生器和master接口状态机两部分组成 mainsmtb.v:在modelsim环境下的仿真激励 top.v设计顶层模块

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