FPGA 蜂鸣器

基于 quartus 2 的 lte 信道估计verilog hdl代码 只有功能仿真 时序仿真自己加sdc文件并且调整testbench的clk才能做出来(Estimated Verilog HDL code based Quartus lte channel only functional simulation timing simulation plus sdc file and adjust the testbench clk to do it)

tPad DE2-115/70开发板可用的摄像头采集、显示程序，QT10.0以上环境可用，原装代码，可以进行修改加以使用，如使用到倒车影像系统中，视频显示等。(tPad DE2-115/70 development board available cameras capture, display program, QT10.0 over the environment is available, the original code can be modified to be used, such as the use of the reversing video system, the video display.)

测量周期,此程序已经在EP2C板子上成功实现(mesure cycle)

AD conversion using LTC1298

说明：  基于FPGA的游戏实例，开发板为Xilinx的basys3，VGA显示(Basys3, VGA Display of Xilinx Development Board Based on Game Example of FPGA)

计算机组成原理的CPU实验，基于quartus平台(CPU experiment of computer organization principle, based on quartus platform)

用fpga芯片使用vhdl语言对AD转换芯片ADC0809进行控制(Using the fpga chip use language of VHDL AD transform chip ADC0809 control)

不同方法实现的CPU系统。同样支持加减乘，逻辑/算术移位，与或非等建议指令。(Different methods to achieve CPU system. Also supports, subtraction, multiplication, logic/arithmetic shift, and the like or recommend instruction.)

说明：  wallance树实现8*8无符号数的相乘(Multiplication of 8 * 8 unsigned numbers by Wallace tree)

用verilog实现的UDP协议，包括arp，udp，ip分段协议等，对于想用FPGA实现TCP/IP协议的人来说，应该会起到一定的帮助作用(Implemented with verilog UDP protocols, including arp, udp, ip fragmentation protocol, etc., who want to achieve TCP/IP protocol with the FPGA people, should play a helpful role)