DE2-115 nios 核网络测试

说明：  Verilog实现按键消抖，工程，已下板验证通过。(Verilog achieves keystroke jitter elimination. The project has been validated on the lower board.)

it shows bcd counter

资源描述描述了PID控制规律及控制器实现及用Simulink建立PID控制器及构建系统模型与仿真方法

可以产生正弦波，三角波、锯齿波、方波，要求频率1Hz-100kHz，步进1Hz，具有自动扫频功能； 正弦波的相位可调，方波的占空比可调； (Can generate sine wave, triangle wave, sawtooth wave and square wave, the required frequency of 1 hz- 100 KHZ, step 1 hz, with functions of automatic frequency sweep The phase adjustable sine wave, square wave duty ratio is adjustable )

一个AXI slave的Verilog实现代码，内部有基于UVM编写的testbench,该slave是基于AXI3协议来实现的，可以给初学者一些启示

使用Verilog HDL 语言在cyclone IV 上实现功能按键控制灯，主要目的是实现按键的消抖程序，加深理解Verilog HDL 语言的并行执行方式

v6 1x 3.125G rapidio协议工程代码(xilinx v6 rapidio data transmission protocol Practical project application engineering code)

通过编写verilog语言完成数据的在液晶LCD1602显示(By writing verilog language to complete the data displayed on the LCD LCD1602)

说明：  一种基于FPGA的调频连续波方位向多通道 FMCW SAR的实时成像信号处理方法及FPGA，包 括：步骤一、计算重构矩阵；步骤二、重构方位向 多通道数据，包括：步骤2 .1、对各个通道的回波 数据沿方位向分别间隔补零，并进行方位向傅里 叶变换；步骤2 .2、将方位向傅里叶变换之后各个 通道方位向相同位置的点组合为一个向量并与 重构矩阵相乘，得到重构完成的方位向数据；(An azimuth multichannel FMCW based on FPGA FMCW SAR real-time imaging signal processing method and FPGA, package Including: Step 1: calculate the reconstruction matrix; step 2: reconstruct the orientation Multichannel data, including: step 2.1, echo of each channel The data is compensated with zero along the azimuth direction respectively, and the azimuth Fourier is carried out Step 2.2, after the azimuth Fourier transform The points of the same position in the channel azimuth are combined into a vector and are connected withThe reconstruction matrix is multiplied to get the reconstructed azimuth data Step 2.3. Repeat step 2.3 for the data of different distance gates)

高速串行设计FPGA-GTX IP设置生成，可动态配置速率2.4Gbps，1.2Gbps，0.6Gbps，自适应链接(High-speed serial design FPGA-GTX IP settings generated dynamically configurable rate of 2.4Gbps, 1.2Gbps, 0.6Gbps, adaptive link)