16位处理器

FPGA上用verilog写的SPWM控制程序，完美运行！自由调试，毕设内容，十分宝贵(The SPWM control program by verilog FPGA perfect run! Free commissioning, Bi-based content, invaluable)

基于BCH码的ECC纠错算法，可纠错2位错误码，供参考(Based on BCH code ECC error correction algorithm, two error codes can be corrected for reference.)

基于FPGA用verilog语言实现16点FFT(16-point FFT FPGA-based verilog language)

vhdl数字电路设计经典教程，入门必备，非扫描版，非常清晰(vhdl digital circuit design classic handbook, entry-essential, non-scan version, very clear)

16QAM调制解调程序画出时域波形、 正交分量、同相分量波形，眼图，散点图等(16QAM modulation and demodulation process to draw time-domain waveform, quadrature components, in-phase component waveforms, eye diagrams, scatter plots, etc.)

this project is based on 2*1 and 4*1 multiplexer and 1*2 and 1*4 demultiplexer using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be used for the final year project for engineering. Here dataflow techniques and behavioural

说明：  SDRAM硬件控制,fpga的verilog语言，适合学习(SDRAM hardware control, Verilog language of FPGA, suitable for learning)

SDIO Verilog Sourcw code

此应用描述了步进式发动机控制器， 你可以控制发动机

应用背景输入向量并行内置自测试（BIST）监测在电路正常运行时执行测试方案不需要设置一个需要设置的电路线来进行测试。这些计划是基于硬件开销和并发测试潜伏期（CTL），即为测试所需的时间完成，而电路工作正常；关键技术内置自测试（BIST）技术构成的一类方案这将提供高性能测试的性能故障覆盖，而同时，他们放松的依赖昂贵的外部测试设备；