MIPS_32位

lap of altera . it s basic about verilog

FPGA设计的四种常用思想与技巧，包括乒乓操作、串并转换、流水线操作、数据接口同步化(FPGA design of the four common ideas and techniques, including the operation of ping-pong, SERDES, pipelining, synchronization of data interface)

CAN驱动器MCP2515驱动，verilog编写，实测可用(CAN driver MCP2515 driver, Verilog written, measured available)

说明：  microsemi的Libero IDE 软件内部IP核详解(Microsemi's Libero IDE software internal IP kernel details)

Quartus2环境下基于VHDL状态机的交通灯程序(VHDL state machine traffic lights based on Quartus2 environment)

代码属于原创，写了一天，比网传的简单明了；用Verilog语言实现的IIC通信协议，用分频计数器的方法实现SCL的输出，同样用计数器的方式确定SCL的低电平中点，在此改变SDA的值。

我必须做智商演示项目。我不知道写代码verilog.so版本请提供matlab和verilog在fpga中的编码实施iq解调器由以下模块组成：射频调制信号、混频器、低通过滤.it包含同相分量、正交分量。

本文为通信专业硕士研究生的毕业论文。主要研究神经网络的FPGA实现及其在网络拥塞控制中的应用。 (In this paper, for the communications professional Master s thesis. Major study of the FPGA realization of neural networks and its application in network congestion control applications.)

针对Altera的DE2/ DE1交互板的音频核心的音频编解码器（编码器/解码器），并提供了音频输入和输出的接口。(The Audio Core interacts with the Audio CODEC (enCOder/DECoder) on the Altera DE2/DE1 Boards and provides an interface for audio input and output.)

说明：  传感器是一种检测装置，能感受到被测量的信息，并能将感受到的信息，按一定规律变换成为电信号或其他所需形式的信息输出，以满足信息的传输、处理、存储、显示、记录和控制等要求(Sensor is a kind of detection device, which can sense the measured information and transform it into electrical signal or other required information output according to certain rules to meet the requirements of information transmission, processing, storage, display, recording and control.)