Xilinx,Altera,ARM,AVR,S52,Lattice等系列FPGA的下载线电路图和PCB

I2C slave 代码，可以完成从机功能-about I2C slave code about I2C slave code

与单片机相比，用CPLD/FPGA器件更适合于直接对高速AD采样控制。本实验接口器件为ADC0809，根据ADC0809的工作时序使用CPLD产生该控制信号，CPLD启动AD转换后，得到的数据送至单片机并在PC机及数码管上显示AD转换结果。(Compared with the microcontroller, CPLD/FPGA devices more suitable for direct sampling control of high-speed AD. The interface of the experimental device for the ADC0809 ADC0809 Timing CPLD is used to generate the control signal, the CPLD to start the AD conversion, the data sent to the microcontroller and the AD conversion result on the PC and digital tube display)

PS2键盘LCD显示控制器的vhdl代码，很难得(PS2LCDController vhdl code)

uart的vhdl实现，包含完整quartus工程文件，相信会有较大帮助-uart vhdl quartus

OFDM完美出图，信噪比，16QAM星座图，加窗信号时域和频域波形图(Perfect figure, OFDM SNR, 16 qam constellation diagram, add window signal time domain and frequency domain waveform figure)

VHDL implementation using mouse and monitor

一个模拟视频输入转VGA视频输出的Verilog程序，视频解码芯片采用ADV7181B，VGA DAC采用ADV7123，强力推荐-an analog video input to VGA video output Verilog procedures, Video decoder chip used ADV7181B, VGA DAC used ADV7123, strongly recommended!

说明：  将BT656数据流转换成RGB图像格式的数据(Converting BT656 data stream into RGB image format)

verilog 简易频率计的设置，包括整个工程(verilog simple frequency meter settings, including the entire project)

单片机通过总线，将占空比和频率送到CPLD/FPGA中，并控制PWM输出.采用Verilog HDL语言编写。(Microcontroller by bus, the duty cycle and frequency sent to the CPLD/FPGA in, and control the PWM output. Using Verilog HDL language.)