Xilinx,Altera,ARM,AVR,S52,Lattice等系列FPGA的下载线电路图和PCB

The red arrow showed the output became 8 when the measured temperature changed to 11°C. As shown by black arrow, the maximum output was 28. The program was run according to the proposed method.

实现米粒状态机 用verilog语言实现状态机的过程(Implement a state machine with a grain of rice verilog state machine language course)

基于FPGA的32阶FIR数字滤波器设计 源程序。设计使用了并行乘法器，运行速度更快，占用内存更小，延迟更小。 (32 order FIR digital filter based on FPGA design source program. Design USES parallel multiplier, faster and less memory, less delay.)

本例是一个6层电梯的控制系统,VHDL原程序,状态机,控制器-This case is a 6-storey elevator control system, VHDL original procedures, state machine, controller

SDR SDRAM 控制器的源代码 altera公司的(source code from altera)

反应速度测试小游戏，最小外设cpld游戏，带设计说明书(Reaction speed test games, the minimum peripheral cpld game, with design specifications)

实现了UART的底层协议，加入了控制器，其波特率可以根据使用进行调整；发送模块、接收模块相互独立，互不影响。(Realization of the underlying protocol UART, joined the controller baud rate can be adjusted according to use transmission module, receiver module are independent of each other.)

一个用VerilogHDL语言编写的多路解复用器-a Verilog HDL language used in the preparation of multi-channel demultiplexer

标准SDR SDRAM控制器参考设计，Lattice提供的verilog源代码-standard SDR SDRAM controller reference design, the Lattice Verilog source code

Top module name : SHIFTER (File name : SHIFTER.v) 2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGHT. 3. Output pins: OUT [15:0]. 4. Input signals generated from test pattern are latched in one cycle and are synchronized at clock rising edge. 5. The SHIFT signal describes the shift number. The shift range is 0 to 15. 6. When the signal RIGHT is high, it shifts input data to right. On the other hand, it shifts input data to left. 7. When the signal SIGN is high, the input data is a signed number and it shifts with sign extension. However, the input data is an unsigned number if the signal SIGN is low. 8. You can only use following gates in Table I and need to include the delay information (Tplh, Tphl) in your design.