vhdl,十进制加减计数器，输出计数序列信号

altera的vga示例

DDR控制器的VHDL源代码.采用FPGA实现DDR接口控制器,适用于Altera的FPGA,最高频率可到100M-DDR controller VHDL source code. Using FPGA DDR interface controller, applicable to Altera FPGA, the highest frequency available 100M

说明：  是基于apb总线下的timer外设的rtl代码，主要包括apb_timer的master逻辑verilog，以及相应的开发文档，包括寄存器的描述，功能特性等。(RTL code is based on timer peripheral under APB bus, which mainly includes master logic Verilog of apb_timer and corresponding development documents, including the description of registers, functional characteristics and so on.)

说明：  FPGA Verilog控制FLASH片外读写(Verilog Controls FLASH Out-of-Chip Read-Write)

无线通信FPGA设计Matlab Verilog代码(Wireless FPGA design Matlab Verilog code)

AD9826中文说明书 ，对于学习AD9826元件有很大的帮助。(AD9826 Discription in Chinese)

VHDL版的C51核(MC8051)-VHDL version of the C51 core (MC8051)

交通灯通过数码管显示，几种模式可调，还可以时间可设，适合初学者入门参考学习。(LED traffic lights can be set to several modes adjustable time beginners reference ~ ~ ~)

利用matlab设计了一个切比雪夫滤波器，并且对滤波器性能进行了仿真分析。(Using the matlab design a chebyshev filter, and has carried on the simulation analysis on filter performance. )

小波变换的VHDL代码，内带正变换逆变换的测试文件。(Wavelet transform VHDL code, with a positive transformation within the inverse transform of the test file.)