用VHDL实现十六位移位乘法器 才有移位相加法来实现

项目目的是设计 DCT 和 IDCT 在 VHDL 中。离散余弦变换图像压缩中用于压缩的 JPEG 图像。此文件包含 DCT 和 IDCT 块和顶级模块于一体的两个块和矢量来测试这两个模块。

cvery high compatibles for quartus

设计一个具有同步置1，异步清零的D触发器。 设计一个类似74LS160的计数器(Design an D trigger with synchronous reset 1 and asynchronous reset. Design a counter like 74LS160.)

FPGA学习的非常好的资料，希望广大朋友都可以学习学习啊(FPGA to learn very good information, I hope our friends can learn ah)

说明：  实现基于黑金开发板的实时时钟功能，显示时分秒(Realize the real-time clock function based on black gold development board, display time, minute and second)

Altera官方FPGA电机控制的中文文档，很不错的参考资料(Altera Official FPGA Motor Control Chinese Document, Good Reference)

detailed spec for Xilinx V5 FPGA, reference for programming of FPGA, system designer or ASIC designer.

LDPC码的FPGA实现，大家相互学习下。。(the code of LDPC implementation by FPGA)

verilog语言实在点变换DFT源代码，可以配合软核或者其他CPU进行综合FFT变换，也可以单独使用生成module！(verilog language is point FFT transform source code, can tie in with the soft-core CPU, or other integrated FFT transform, it can be used to generate module!)

Syplify经典英文教程。内含众多实验例程，Lab 1 Basic Synplify Run；Lab 2 Analyzing Critical Path and Assigning Timing；Lab 3 FSM (Finite State Machine) Compiler Constraints and Attributes(Syplify classic English tutorial. Contains numerous experiments routine, you can help learners to quickly grasp Syplify tips, is a rare foreign experiments tutorial.)