1 第二个计时器 impliomentation vhdl

Xilinx FPGA make 50 smaller-Xilinx FPGA make 50 smaller

HLD开发语言ADHL介绍。ADHL是ALTERA公司开发的硬件描述语言，也是一种较为流行的开发工具。是介绍AHDL的入门培训资料。-HLD development language ADHL introduction. ADHL is ALTERA developed hardware description language, but also a more popular development tools. AHDL is the introduction of induction training information.

Multi-Digital Down Converter design.

Quartus II 7.2环境中，采用硬件描述语言VHDL独立完成了基于MIPS指令集的32位RISC处理器的逻辑设计(quartusII mips pipeline 32bit cpu design)

Xilinx ISE 9.2 and ChinpScope Pro 9.2 Sn

说明：  ZEDBOARD的管脚分配图和约束文件，包括PCB图和xdc文件(Pin assignment of ZEDBOARD)

UART自适应波特率发生器，其中是以文档的形式来介绍怎样实现UART波特率发生器的实现(Adaptive UART baud rate generator, which is in the form of a document to describe how to achieve the realization of UART baud rate generator)

说明：  基于altera fpga的fir IP核实现希尔伯特变换，有matlab仿真(Based on Altera FPGA fir IP core to achieve Hilbert transform, matlab simulation)

c语言编写51单片机键盘扫描程序，方便移植到其他的硬件上去-51 Singlechip c language keyboard scanning procedures for transplantation to other hardware up

VHDL设计的功能齐全的交通灯程序，经过仿真一切功能符合要求。-VHDL