这是一个控制芯片CPLD 1394的verilog程序，可以参考应用。

用verilog写的4*4小键盘按键检测程序。本工程已经编译好。可以直接在Atera DE1 Fpga开发板上运行-Written using Verilog 4* 4 keypad keys detection procedures. The project has been compiled. Directly in the development of Atera DE1 Fpga board run

VHDL经典教程,下了不会后悔-VHDL Tutorial classic, the next will not regret it

一个比较有参考价值的sram IP核，对SOPC感兴趣的人士有一定的指导意义！该程序是采用avalon总线，可以直接内嵌进SOPC Builder。-A comparison reference value has sram IP core, on the SOPC interested people have a certain guide! The procedure is used avalon bus, can be directly embedded into the SOPC Builder.

一个可以综合的Verilog 写的FIFO存储器 内附文档说明-a comprehensive Verilog can write FIFO memory attached document shows

100个VHDL的例子-100 examples of VHDL

数字钟：实验中用到的小程序，用于万年历中的模块(Digital clock: a small program used in the experiment, the modules for calendar)

串口收发，实现可调波特率的串口通信，verilog源码(Serial port and transceiver)

说明：  自己设计的一个其人投票系统，对于VHDL初学者可以参考下(One of their own design their human voting system, for VHDL beginners can refer to the following)

master spi的源代码（verilog），包括文档，测试程序(master spi the source code (verilog), including documentation, testing procedures)

使用verilog语言，滚动显示“verilog”字符串程序代码及相关说明(Using verilog language, scrolling display " verilog" string code and instructions)