这是一个控制芯片CPLD 1394的verilog程序，可以参考应用。

编译实现循环码的产生，用FOR循环分别对其中的码元进行设置。-Implementation cycle of the compiler generated code, respectively, using FOR Cycle one of the key element of the set.

Xilinx ISE 9.2 and ChinpScope Pro 9.2 Sn

高精度直流信号源，DAC1220，20位分辨率，双极性输出(High-precision DC source, DAC1220,20 bit resolution, bipolar output)

这是基于Quartus2 开发环境和verilog hdl语言写的38译码器(This is based development environment and Quartus2 verilog hdl language used to write decoder 38)

本代码实现了486总线的功能，初学者可以借鉴学习-This code implements the 486 bus functions, beginners can learn to learn

Verilog投币式手机充电仪 清华大学数字电子技术基础课程EDA大作业。刚上电数码管全灭，按开始键后，数码管显示全为0。输入一定数额，数码管显示该数额的两倍对应的时间，按确认后开始倒计时。输入数额最多为20。若10秒没有按键，数码管全灭。(Verilog coin operated cell phone charger EDA major homework of digital electronic technology foundation course, Tsinghua University. Just put on the digital tube completely extinguished, press the start button, the digital tube display is 0. Enter a certain amount, the digital tube shows the amount of double the corresponding time, according to the confirmation began countdown. The maximum amount of input is 20. If there is no button in 10 seconds, the digital tube will die out.)

一个用Verilog编写的编帧、解帧及码速匹配的程序，相当经典(Verilog prepared with a series of frames, frames and solutions yards speed matching procedures, rather classic!)

哈希算法FPGA实现代码，采用MD5算法，并给出了仿真波形。(MD5 hashing algorithm for FPGA implementation code)

本程序实现流水线功能，您可根据自己需要更改参数，试用芯片xilinx，用verilog语言编写(This program implements the pipeline, you may be required to change the parameters according to their own try xilinx chip with verilog language)

FPGA TW2867输入到ADV7171显示实验(FPGA TW2867 input to the ADV7171 display experiment)