这是一个控制芯片CPLD 1394的verilog程序，可以参考应用。

A latch3 written in VHDL.

IIC slave controller source code

应用背景在本文中，我们提出了一种高效的非流水线式AES-128实现高实施吞吐量，以便它可以使用在千兆协议。我们实现我们的AES-128加密设计在Xilinx Virtex-7 FPGA解密了4.86 Gbps的5.30/ ECB模式和5.23/4.84吞吐量在CBC模式Gbps。关键技术由于高吞吐量的要求加密信道的体系结构，一种高效的实施硬件是必要的。这可以实现通过使用高端可重构智能利用平台。实现令人信服的高吞吐量，一高效的非流水线式的先进实现数据加密标准（AES）和密钥长度为128比特，用于千兆位现场可编程门阵列（FPGA）协议提出。

VHDL Code For Full Adder By Data Flow Modelling

Verilog实现的NOR FLASH控制器，基于M25P128开发，功能完整，简洁易懂，自用无问题。(Verilog implementations NOR FLASH controller, based M25P128 development, full-featured, easy to read, for personal use, no problem.)

基于sopc技术的数字均衡器带通滤波器及12864液晶显示-Sopc technology-based digital equalizer band-pass filter and liquid crystal display 12864

maxplus2为开发环境 vhdl编写的 扫描 程序-maxplus2 VHDL development environment for the preparation of a scanning program

通过配置DS1302芯片来实现实时时钟的监测，我们通过通过控制2个按键来选择我们要在数码管上显示的时间，按下按键1我们来显示周几，按下按键2来显示年月日，不按显示时分秒，这样显示复合我们的数字表的显示(By configuring DS1302 chip to monitor the real-time clock, we select the time that we want to display on the digital tube by controlling 2 keys. Press key 1 to show the week, press the key 2 to show the year and month, not according to the display time, so that the display of the display of the display of our digital table.)

Spartan® -3E 现场可编程门阵列家族是为满足对成本敏感的消费电子大量应用的需要 而特别设计的。 (Field Programmable Gate Array family needs is to meet the cost-sensitive applications, a large number of consumer electronics Specially designed.)

《无线通信FPGA设计》包含的所有例子源码，包括matlab仿真和verilog源码，本书内容还是非常丰富的，涉及无线通信领域各个方面。不过对于一些比较新的技术，其FPGA实现部分过于简略，难以在工程中实用化。(" Wireless FPGA Design" contains all the examples source code, including the matlab simulation and verilog source code, the contents of this book is still very rich, involved in all aspects of the field of wireless communications. But for some relatively new technology, some of its FPGA implementation is too brief, it is difficult in practical engineering.)