FIFO_design

说明：  FPGA核心板EP4CE10F17C8电路原理图(Circuit schematic diagram of EP4CE10F17C8 core board of FPGA)

自己编写的DDS发生器，方波、三角波、正弦波、还可以输入任意的波形文件

When the initial input falls between the Switch off point and Switch on point values, the initial output is the value when the relay is off.

近年来随着物联网技术的发展，传感器广泛应用在各种领域，如环境监测，等在消费电子领域，如智能手机，为用户更极端的经验，各种传感器添加到手机，随着传感器数量和种类的增加，手机电池严重测试电池寿命，基于此，最新研究的一种新技术——sensorhub技术有望改善这一问题。文件是使用FPGA设计格sensorhub源代码，希望和大家一起交流。

密码锁verilog源代码，包括四个七段数码管显示模块，设置密码以及输入密码校验模块(Password lock Verilog source code, including four of seven digital tube display module, set the password and password verification module)

此源码为线性相位滤波的vhdl源码与设计心的体会，理论分分析与工程实践总结相结合，有非常大的参考价值 可直接使用。 (The source for the linear phase filter VHDL source code and design of the heart experience, theoretical analysis to summarize the combination of engineering practice, a very large reference value can be used directly.)

说明：  用FPGA于32进行SPI单向通信，FPGA向32放松发送数据(One-way SPI communication is carried out in 32 with FPGA, and data is sent to 32 with ease by FPGA.)

说明：  运用VHDL描述函数发生器的各个波形，可有构成多功能函数发生器。(VHDL description of the use of various function generator waveforms, can constitute a multi-purpose function generator.)

数控分频器的设计 数控分频器的功能就是当在输入端给定不同输入数据时，将对输入的时钟信号有不同的分频比，例3的数控分频器就是用计数值可并行预置的加法计数器设计完成的，方法是将计数溢出位与预置数加载输入信号相接即可。(NC NC divider divider design of its function is when the input given different input data, input the clock signal will have different frequency than, for example 3 is to use the NC prescaler count preset value of the adder parallel counter design is completed, the method is to count the number of overflow bit with preset load to the input signal phase.)

流水线LMS，和RLS算法的Verilog代码，用于自适应信号处理的FPGA实现。(The Verilog code about fir_pipline_lms and fir_rls. They commonly used in adaptive signal processing in FPGA platform.)