Altera公司提供的千兆网程序

数字时钟管理器，xilinx公司开发板集成时钟，实现分频、倍频等功能。(Digital clock managers, xilinx development board integrated clock divider, multiplier, and other functions.)

该程序用vhdl编写的vga显示的小游戏，到时屏幕上会显示一个小球，一根棒子，一面墙，棒子可以通过按键控制来移动。而小球在不停的运动，遇到墙会反弹。(Game written by the program with VHDL VGA display, the screen will display a small ball, a stick, a wall, stick to move through the key control. Ball in constant motion, encountered the wall will bounce.)

产生SH,SP,RS,SP,φ1,φ2驱动脉冲，用于驱动TCD1501的的源代码(To generate SH, SP, RS, SP, φ1, φ2 drive pulse for driving TCD1501 source code)

用verilog实现的buffer，经过了fpga平台验证。(Implement buffer with verilog.)

rc6 algorithm designed based on verilog and is verified

this project is about FIR FIlter By VHdl codes in the ISE.

MIPS 处理器程序，出自于《CMOS VLSI Design and Systems Perspective》书中。可以实现LB、SB、RTYPE、BEQ、J指令，仿真测试可以用。

说明：  由忆阻器机制设计蕴含逻辑，内含testbench仿真文件(Design implied logic by memristor mechanism, including testbench simulation file)

verilog描述的基于LMS的自适应噪声消除器ANC算法。用于数字音频处理。(The verilog Description LMS-based adaptive noise canceller ANC algorithm. For digital audio processing.)

IIC驱动 verilog代码 ！！！！！！！！！！！！！ 开发板测试正常！！！！！！！！！！！！！！！！！