这是一个在FPGA上实现CRC算法的程序，包含了CRC

关于语音通信信道调制的程序代码，是论文的仿真程序(About voice communication channel modulation code, the authors of the paper simulation program)

数字逻辑课程设计，用vhdl实现红外线传输系统的课程设计，下载验证通过-Digital logic course design, using vhdl infrared transmission system to achieve curriculum design, download verified by

实现扰码的功能，主要为64位在pcs子层传输的扰码器设计(To achieve the functions of scrambling code)

传感器是一种检测装置，能感受到被测量的信息，并能将感受到的信息，按一定规律变换成为电信号或其他所需形式的信息输出，以满足信息的传输、处理、存储、显示、记录和控制等要求(Sensor is a kind of detection device, which can sense the measured information and transform it into electrical signal or other required information output according to certain rules to meet the requirements of information transmission, processing, storage, display, recording and control.)

USB 1.1 IP-CORE和设计范例 VHDL源代码-Sample program for USB1.1 IP core design, VHDL source code

基于verilog hdl编写的FPGA正弦信号发生器，已测试。(FPGA sine signal generator)

迫零-串行干扰删除检测的程序，包括16QAM和QPSK(Zero forcing- Interference Cancellation detection procedures, including 16QAM and QPSK)

HSSDRC IP core is the configurable universal SDRAM controller with adaptive bank control and adaptive command pipeline. HSSDRC IP core and IP core testbench has been written on SystemVerilog and has been tested in Modelsim. HSSDRC IP core is licensed under MIT License

vhdl code for GIF Image Viewer

高精度直流信号源，DAC1220，20位分辨率，双极性输出(High-precision DC source, DAC1220,20 bit resolution, bipolar output)