Verilog LED 斯巴达 6

hi this is an verilog codes

《Altera FPGA_CPLD设计 高级篇》详细介绍FPGA应用于高级特性，LogicLock设计，时序约束，设计优化，高级工具及系统级设计技术，是深入学习FPGA的重要材料(" Altera FPGA_CPLD advanced part design" details FPGA used in advanced features, LogicLock design, timing constraints, design optimization, system-level design tools and advanced technology, in-depth study is an important material for FPGA)

数字乘法器，作为现代计算机中必不可少的一部分，其设计工作越来越受到人们的重视。本文采用硬件描述语言verilog HDL设计了一个基于补码一位乘法的浮点乘法器，设计功能完善，灵活性较好。理论依据包括浮点运算和补码一位乘法运算。本文对开发环境，测试环境做了简要介绍，并对设计过程进行了详细的描述分析，使用Modelsim软件的Simulator模块进行了功能仿真

利用systolic_arry实现矩阵的乘法/求逆等操作  矩阵为4*4矩阵   所发压缩包为ISE14.6的整个开发工程。

agilex fpga description

说明：  这是8位CPU的CVDL代码。CPU 的主要功能是执行指令，控制完成计算机的各项操作，包括运算操作、传送操作、输入/输出操作等。作为模型计算机设计，将重点放在寄存器级，采取较简单的组成模式，以尽量简洁的设计帮助学生掌握CPU 的基本原理。 此次设计CPU就是为了了解CPU运行的原理，从而完成从指令系统到CPU的设计，并且通过仿真对CPU设计进行正确性评定。(The main function of CPU is to execute instructions, control and complete various operations of computer, including operation, transfer operation, input / output operation, etc. As a model computer design, it focuses on register level and adopts a simpler composition mode to help students master the basic principles of CPU with a concise design as far as possible. This design of CPU is to understand the principle of CPU operation, so as to complete the design from instruction system to CPU, and evaluate the correctness of CPU design through simulation.)

基于FPGA的1602时钟显示,驱动1602显示时钟,矩阵键盘调时(1602 FPGA-based clock display, clock display driver 1602, when the transfer matrix keyboard)

基于 hdl语言的re232通信实验的设计，程序简单明了，一学就会(rs232 communication)

it is a filter contract VHDL .(it is a filter contract VHDL.)

VGA controller : Genarate a VGA signal from your inout information as color info of each pixel