verilog写sober边缘检测

很好的学习FPGA嵌入式的资料！适合初学者和工程师参考！(Good learning FPGA embedded information! Suitable for beginners and engineers reference!)

利用平方环法提取同步载波的FPGA实现的仿真(FPGA implementation of synchronous carrier extraction using square loop method)

4 级流水方式的8 位全加器。。。。。。(Way flow of 4 full adder 8. . . . . .)

出租车计费，器设计一个出租车自动计费器，计费包括起步价、行车里程计费、停止和暂停不计费三部分。现场模拟汽车的启动、停止、暂停和换挡状态。分别用四位数码管显示金额和里程，各有两位小数，行程 3公里内，起步费为6元，超过3公里，以每公里1.3元计费(Car repair billing device)

能够实现16位的SDRAM的读写，没有仿真文件，只有SDRAM读写的源代码，用Verilog编写(can complete read or write sdram， only include Verilog code and no simulation files)

一种十字路口交通灯在matlab环境中的实现源码(Traffic lights at the crossroads)

液晶显示屏显示汉字“年”的驱动程序VHDL(nian VHDL)

说明：  PIC单片机学习软件及其资料，入门到精通(PIC MCU learning software and its information, entry to proficiency)

1、用状态机设计A/D转换器ADC0809的采样控制电路，并在数码管上显示转换结果； 2、设置有复位和启动/保持开关，要求 ⑴ 复位开关用来使A/D转换器复位，并做好A/D转换准备； ⑵ 启动/保持开关用来控制A/D转换器开始连续转换或停止转换保持结果，即按一下启动/保持开关，启动A/D转换器开始转换，再按一下启/停开关，停止转换并保持结果。 3、采用Verilog HDL语言设计符合上述功能要求的控制电路。(1, with the state machine design A/D converter ADC0809 sampling control circuit and display the results on the digital conversion 2 is provided with a reset and start/hold switch, reset switch is used to make the request ⑴ A/D converter reset and do A/D conversion ready ⑵ start/hold switch is used to control the A/D converter starts converting or stop the conversion to maintain a continuous result that by clicking Start/hold switch, start the A/D converter to start the conversion, and then Click the start/stop switch stops the conversion and keep the results. 3, using Verilog HDL language designed to meet the functional requirements of the above-mentioned control circuit.)

浮点数 矩阵乘法模块 verilog语言编写 可直接调用(Floating-point matrix multiplication module can directly call verilog language)