verilog写sober边缘检测

说明：  DFT FPGA实现,simulink到vivado(DFT FPAG implement base on simulink and HLS)

FPGA中常用的上升沿检测和下降沿检测代码以及检测是否有边沿，使用的verilog hdl语言，有几个写法，附带仿真时序，可以下载学习一下

基于fpga与verilog语言的的sdram读写(SDRAM reading and writing based on FPGA and Verilog language)

The objective of this project is to design and implement the controller for an electronic safe. You will interface a 16-button keypad to the NIOS boards. The combination code of the safe will be the last

PC104总线的CPLD代码，调试已经通过，可以修改应用到其他的工程(PC104 bus CPLD code, debugging has been passed, you can modify the application to other engineering 示例用法:)

利用FPGA通过IDE PIO模式实现读写CF卡桥接，可使用ARM或DSP等处理器通过FPGA来CF卡读写CF卡，读数据可以达到30MB/s，写数据10MB/s。

全自动洗衣机的控制器。 1.洗衣机的工作步骤为洗衣、漂洗和脱水三个过程，工作时间分别为：洗涤10秒，漂洗5秒，脱水5秒； 2.用一个按键实现洗衣程序的手动选择：A、单洗涤；B、单漂洗；C、单脱水；D、漂洗和脱水；E、洗涤、漂洗和脱水全过程； 3.用显示器件显示洗衣机的工作状态（洗衣、漂洗和脱水），并倒计时显示每个状态的工作时间，全部过程结束后，应提示使用者； 4.用一个按键实现暂停洗衣和继续洗衣的控制，暂停后继续洗衣应回到暂停之前保留的状态； (Automatic washing machine controller. 1 washing machine work steps for the laundry, rinsing and dehydration three processes, working hours are as follows: washed for 10 seconds, rinse for 5 seconds, dehydrated five seconds 2 with a button to manually select the program to achieve laundry: A, single-washing B, single rinse C, a single dehydration D, rinsing and dehydration E, washing, rinsing and dehydration the whole process 3 with a display device display the working status of washing machine (laundry, rinsing and dehydration), and each state countdown show working hours, after the whole process should prompt the user 4 laundry with a button to pause and continue control of laundry, laundry should be back after a pause pause before continuing to retain the state )

使用matlab的simulink工具滤波器功能实现了FIR系数的计算，同时使用verilog hdl实现了功能仿真，通过调试在Xilinx的ZEDBOARD板子上实现了结果，使得FIR的应用得以在硬件上实现，调试和注解有写。

说明：  Verilog AXI Components Readme GitHub repository: alexforencich verilog-axi

altera官方的各种有用的参考资料，都是自己收集的，遇到问题可以很方便的查看(altera official variety of useful references, are their own collection, problems can easily view)