ADC CS5368驱动

用fpga实现的连连看游戏，功能还不完善，不过可以借鉴。(Realize with FPGA Lianliankan game, function is not perfect, but can be used for reference.)

16QAM调制解调程序画出时域波形、 正交分量、同相分量波形，眼图，散点图等(16QAM modulation and demodulation process to draw time-domain waveform, quadrature components, in-phase component waveforms, eye diagrams, scatter plots, etc.)

数字电压表的实现，VHDL语言实现，AD采用TLC549，通过学习，了解AD采集过程(The realization of digital voltage meter, VHDL language, AD using TLC549, by learning to understand the acquisition process AD)

利用FPGA控制VGA显示器显示字符汉字的程序，里面有注释。(VGA display with FPGA control procedures Kanji characters, there are comments.)

它是基于Verilog硬件描述语言浮动乘法器的数字化设计。该设计可以实现全功能，是更好的灵活性，其理论基础上浮动计算并补偿位移倍增。

RS编码是一种纠错码，本程序实现RS（255，223）用FPGA 实现RS编码，程序在Quartus II中调试通过。(RS coding is an error-correcting codes, the procedures for the realization of RS (255,223) with FPGA realization of RS codes, in the Quartus II program through the debugger.)

FFT的MATLAB实现。非常完整的实现FFT过程，速度很快。(The FFT in MATLAB. Contains more than one source, the FFT process. Learning Reference essential)

说明：  完成对cdcm6208的时钟芯片的配置，输出高频时钟(cdcm6208 cofigure using SPI interface)

该程序是一个可完成订制化的SPI双向总线接口，时钟相位、极性，以及分频比全部可通过寄存器进行配置，已经在ISE下通过综合，占用资源少，强烈推荐 (The program is a complete custom of SPI bidirectional bus interface, clock phase, polarity, and the divider ratio can all be configured through the register, has been in the ISE through an integrated, small footprint, it is strongly recommended)

用verilog语言实现的除法器，实现方式为移位减