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AHB 总线slave verilog实现(Implementation of AHB bus)

用于数字积分器的设计，主要涉及VHDL、Verilog等FPGA编程语言。(Design of Digital Integrator)

Disparity mapp code in VHDL

该资料基于FPGA实现USB2.0的高速传输，即CY7C68013A芯片的数据传输，包括FPGA与上位机之间数据的相互传输，CY7C68013A的传输速率最高可达480M/S。(The FPGA-based high-speed data transmission USB2.0, that CY7C68013A chip data transmission, including the mutual transmission of data between the FPGA and the host machine CY7C68013A transfer rate up to 480M/S.)

在MATLAB下自编实现快速傅里叶分析，(Fast fft own procedures, faster than the system call fft slowe)

说明：  串口操作源代码，本代码采用veilog hdl语言编写，并经过本人多次验证。(source code, the code used veilog HDL language, and after I repeatedly verified.)

this project is about FIR FIlter By VHdl codes in the ISE.

基于FPGA开发的均值滤波程序，效率很高，非常有用(Based on FPGA development of the mean filter program)

利用verilog语言实现了SHA-1机密算法，具体算法与加密芯片ds28e01一致。(Using Verilog to achieve the SHA-1 secret algorithm, the specific algorithm is consistent with the encryption chip ds28e01.)

G.hnMAC层功能代码，实现了MPDU的资源调度(G.gn MAC codeG.gn MAC codeG.gn MAC code)