LDPC码校验节点（checknode）进行奇偶校验方程时的vhdl编程，硬件语言实现...

xc2s100E FPGA的原理图 给想涉足FPGA的新人参考-xc2s100E FPGA schematic diagram of the FPGA would like to set foot in the new reference

高速串行设计FPGA-GTX IP设置生成drp模块，可动态配置速率2.4Gbps，1.2Gbps，0.6Gbps，自适应链接(High-speed serial design FPGA-GTX IP setting generation drp module, dynamically configurable rate 2.4Gbps, 1.2Gbps, 0.6Gbps, adaptive link)

verilog实现ALU的源代码，并提供了一个详细的测试平台！-achieve ALU Verilog source code, and provide a detailed test platform!

高速高性能FFT处理器的VLSI实现研究，适合做FPGA的技术人员参考研究FFT-High-speed high-performance FFT processor VLSI realization of research, suitable for FPGA technology reference study FFT

非常多的verilog实例，对于刚入门者比较有用-lot of verilog example, just beginners more useful

对pci9054芯片的配置进行了设置，并对PCI9054的各状态机进行了设置，程序经过了测试(Pci9054 chip on the configuration of the set, and each state machine PCI9054 been set, the program have been tested)

用FPGA实现sos摩尔密码，即输出电平信号短长短。就是有次序的控制输出莫斯密码的“点”，“画”和“间隔”。而 control_module.v 是一个简单的定时触发器，每一段时间都会使能sos_module.v。(Realized by FPGA sos mole password, the output signal level of short duration. There is a sequence of output control points Moss password, painting and intervals. And control_module.v is a simple timer triggers, each period of time will enable sos_module.v.)

ADC7606的驱动代码，采用verilog实现(ADC7606 driver code, using Verilog to achieve)

cyclone3_handbook-datasheet

以ISE为开发环境，Verilog语言编写程序。功能：FPGA控制 LCD_1602动态显示秒表(In the development environment of ISE, Verilog language is used to write programs. Function: LCD_1602 dynamic display stopwatch controlled by FPGA)