LDPC码校验节点（checknode）进行奇偶校验方程时的vhdl编程，硬件语言实现...

this project is based on sr and d flip flop using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be used for the final year project for engineering. Here dataflow techniques and behavioural -this project is based on sr and d flip flop using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be used for the final year project for engineering. Here dataflow techniques and behavioural

八位并行数据转换为串行数据依时钟信号串行输出(Eight bit parallel data to serial data)

说明：  vivado的license ,可以用在2019.1,2019.2,在win10 64bit上已检验过.(It can used in vivado2019.1,2019.2)

FPGA实现乒乓球游戏 代码及仿真 VGA实现(FPGA realizes table tennis game code and simulation VGA implementation)

利用c控制adc，主要是控制字写入，状态控制。-C control the use of adc, is mainly controlled write, the state of control.

PC104总线的CPLD代码，调试已经通过，可以修改应用到其他的工程(PC104 bus CPLD code, debugging has been passed, you can modify the application to other engineering 示例用法:)

通过modelsim仿真检测matlab生成滤波器效果。(Generate the filter through matlab and simulated by modelsim.)

VGA显示原理与VGA时序实现论文,详细介绍了VGA的原理 (Principle and VGA VGA display timing to achieve paper, detailing the principles VGA)

用Vivado IPI搭建的Zynq-7000 PS到PL通信过程，使用了AXI-HP接口，利用AXI-DMA IP实现直接读写DDR的过程，软件可以配置传输尺寸。(The Zynq-7000 PS to PL communication process is built by Vivado IPI. AXI-HP interface is used, and AXI-DMA IP is used to read and write DDR directly. The software can configure the transmission size.)

说明：  credit base network on chip(network on chip (noc))