闩锁、 人字拖鞋和记数器-DE2-115

能够在EDA环境下实现四位十进制数字密码锁的设置与开锁功能，并能更改使用密码，还可以防止抖动(EDA environment to achieve four decimal code lock and unlock function of the settings and change the use of passwords, but also to prevent the jitter)

频率计，测量频率。可测范围为100HZ至60khz.测量比较稳定。基于MSPg2553(Frequency meter, measuring frequency. Measurable range 100HZ to 60khz. Stable measurement)

24,60,100进制的计数器，还有数字时钟，欢迎下载哦~-24,60,100 229 of the counter, digital clock also welcome to download oh ~

说明：  FPGA按键延时模块，产生key_value和key_flag 可直接例化调用(The key delay module of FPGA)

说明：  电网协议信道解交织器设计FPGA实现，适用于PB16的宽带电力线载波通信(Grid protocol channel deinterleaver design FPGA implementation, suitable for PB16 broadband power line carrier communication)

vhdl寄存/计数器设计-VHDL Storage/counter design

基于数码管独立显示和三色灯的交通指示系统设计(Design of Traffic Indicator System Based on Digital Tube Independent Display and Tri-color Lamp)

nios学习资料，fpga调用外部sdram实例，值得初学者下载。(nios learning materials, fpga call external sdram instance, it is worth beginners to download.)

实现扰码的功能，主要为64位在pcs子层传输的扰码器设计(To achieve the functions of scrambling code)

该工程描述的是一位全加器，可以用此作为基础，搭建多位全加器(The project description is a full adder can use this as a basis to build a number of full adder)