Verilog ADPLL文件和testbench。V

基于FPGA实现交织 在通信中交织的算法 已在板上通过测试(based on FPGA to Interleaver)

vhdl抗抖动滤波器的设计，包括完整的工程-VHDL anti-jitter filter design, including the complete works

实现QPSK系统的调制解调仿真，基带成形滤波器采用升余弦滚降滤波器，将仿真的误码率与理论误码率作了比较(Implement QPSK modulation and demodulation simulation system, the baseband shaping filter using Raised Cosine filter will BER simulation were compared with the theoretical BER)

SPI接口的实现以及对外设的读写操作，其中包扩了几种工作方式，同时可以读取外设的版本号，传输速率可以达到2Mbps-SPI interface implementation, as well as read and write operations on the peripheral, which extended several work packages at the same time can read the version number of peripherals, transfer rate up to 2Mbps

本白皮书探讨了在PCI Express的因素 技术可能会影响性能。它还 提供指导如何估算 的系统性能。(This white paper explores the factors in PCI Express technology may affect performance. It also provides guidance on how to estimate the system performance.)

protel fpga常用封装库1，非常难找的-protel fpga library a popular package is very difficult to find the

24秒倒计时系统（有跑马灯） 利用CPLD-24 seconds remaining systems (5,250) using CPLD

说明：  I2C读程序，通过状态机描叙,仿真达到要求(I2C Reading, depicts through the state machine, called Simulation)

这个我也太清楚是什么 反正师兄们说有用 发大家-I am also very clear that what is useful anyway, say senior U.S. fa

闹钟设计，VHDL，源代码。闹钟设计，VHDL，源代码。(Alarm clock design, VHDL, the source code.)