Verilog ADPLL文件和testbench。V

VHDL实现的8位乘法器，所有仿真全部通过-VHDL to achieve 8-bit multiplier

LCD Interface_Xilinx.CPLD源码参考设计(LCD Interface Xilinx CPLD)

此为华远显示320*240LCD驱动程序，该程序也适用于带RA8806控制器的LCD(This is the Huayuan display 320* 240LCD driver, the program also applies with RA8806 LCD controller)

library of protues aaaaaaaa

CH341A的I2C接口Labview all vision (CH341A I2C Labview)

CH2CH1VHDL 数字电路参考书所有程序4-CH2CH1VHDL digital circuit reference all proceedings 4

带有异步清零、异步置位功能的边沿JK触发器(With asynchronous reset, asynchronous setting function of edge JK flip-flop)

VHDL Design of BCD to 7-segment decoder using PROM

FPGA板上的锁存器PLL控制代码（verilog代码）(FPGA board latch the PLL control code (Verilog code))

本源码为Nios II的开发示例,主要演示基于Nios II的uCOS的移植。开发环境QuartusII。 本示例十分经典，对基于SOPC开发的FPGA初学者有很大帮助。(The source code for the Nios II development of examples, mainly based on the Nios II shows the uCOS transplant. Development environment QuartusII. This example is very classic, FPGA-based SOPC development of great help for beginners.)