用VHDL的玛摩尼的ASIC设计

一个简单的uvm搭建的ahb简单实例,包含了各个组件以及编译的运行的脚本(one sample example about ahb，include every component and compile script)

LDPC码不同码长对比。码率选择1/2.码长分别为256，512，1024.(LDPC codes of different code length contrast. Bitrate select 1/2 yards long were 256,512,1024.)

FPGA，用VHDL语言产生可调的PWM波(FPGA, VHDL language adjustable PWM wave)

It is Synopsys dmac controller databook

说明：  serdes中的8B/10B编码 verilog实现(Implementation of 8B / 10B coding Verilog)

FIR滤波器的VHDL语言实现-The implement of FIR Filter based on VHDL

RS编码器在fpga上的实现，用的modelsim开发环境(RS encoder in the realization of the fpga, development environment used in modelsim)

说明：  KMP算法的Verilog HDL实现，模式串从模块的外部输入，计算next函数，然后进行KMP匹配。有仿真。环境为Quartus II 8.0 Web Edition。(Verilog HDL implementation KMP algorithm, pattern string from the module' s external input, calculate next function, then KMP matching. A simulation. Environment for the Quartus II 8.0 Web Edition.)

说明：  使用Verilog，以Quartus II 为平台，编写了一个DDS信号发生器程序。(Using Verilog and Quartus II as the platform, realizing the DDS signal generator program .)

Efficient CIC filter Implementation using VHDL