用VHDL的玛摩尼的ASIC设计

说明：  这是一个用Verilog语言编写的一组程序，主要是熟悉开发板的应用，以及verilog语言(This is a Verilog language with a set of procedures, mainly familiar with the application development board, and the verilog language)

verilog hdl教程135例:verilog hdl语言类似于C语言，便于学习。本文档带有源代码，3-6章-Verilog HDL 135 cases Guide : Verilog HDL language similar to the C language, to facilitate learning. This document with the source code, 3-6

Xilinx的I2C总线控制器，verilog版本，文档号是XAPP333，可到Xilinx网上查找具体说明，有对应的VHDL版本的-Xilinx

通信基带信号发生器的设计，采用单片机输入频率和波形，在FPGA中实现频率和波形生成-Communications base-band signal generator design, the use of single-chip input frequency and waveform, in the FPGA to achieve the frequency and waveform generation

用FPGA控制1602型液晶显示，显示一行英文语句。(show)

本文参考了Xilinx 官方文档UG873，“System Design Using Processing System High Performance Slave Port”。主要实现了PL 中AXI CDMA IP 与PS 部分HP64bit 从接口集成。 本例中AXI CDMA 部分扮演主机，从PS 部分DDR 系统内存中源缓冲区拷贝一列数据到目 的缓冲区。可以分别采用裸机工程和基于Linux 的应用软件来实现功能。(This reference to the official document Xilinx UG873, " System Design Using Processing System High Performance Slave Port" . The main achievement of the PL in AXI CDMA IP interface integration with PS part HP64bit. In this example AXI CDMA part to play host, a copy of a column of data into the destination buffer section PS source DDR system memory buffer. Can respectively bare engineering and Linux-based applications to achieve functional.)

本程序是锁相环的仿真程序，具有接收端载波同步的功能。注释详尽，程序规范。发端的调制方式有单载波调制，BPSK调制，QPSK调制可供选择。程序中有星座图，锁相环的频差、相差图，以及解调后的基带波形。(This program is a phase-locked loop simulation program, the with carrier synchronization receiving end function. Notes detailed program specifications. The originator of the modulation scheme to choose a single carrier modulation, BPSK modulation, QPSK modulation. Program constellation diagram, the PLL frequency difference, a difference of FIG, and the demodulated baseband waveform.)

说明：  FPGA实现四位数与四位数乘法，有仿真波形，合理利用FPGA资源(Four-digit and four-digit multiplication is realized by using FPGA. It has simulation waveform and makes rational use of the resources of the FPGA.)

this come from alter ,you can look and find it on line.

低通滤波器在QUARTUS7.0开发环境下的文本与框图结合的实现方法的源代码-Low-pass filter QUARTUS7.0 development environment in the text and diagram combination of methods to achieve source code