关于格 CPLD ufm 演示

altera fpga ep3c25器件微处理器开发，niosii+sram, 已编译通过，可直接下载到开发板(altera fpga ep3c25 the development of microprocessor devices, niosii+ sram, compiled through, can be directly downloaded to the development board)

基于VHDL语言的七段显示管程序， 实现9个数字循环 并且能控制播放速度(SEVEN SEGMENT DISPLAY)

《CPLDFPGA嵌入式应用开发技术白金手册》源代码，涉及FPGA/CPLD的各个方面，键盘扫描，LED扫描等简单程序及滤波器等的设计(" CPLDFPGA platinum embedded application development technology handbook" source code, related to FPGA/CPLD all aspects of the keyboard scanning, LED scanning filters, such as simple procedures and design)

说明：  基于FPGA的信号发生器，产生了正弦波，方波，锯齿波和三角波四种波形，按下一次按钮，波形切换一次。按下另一个按钮，改变波形的频率(The signal generator based on FPGA can generate four kinds of waveforms: sine wave, square wave, sawtooth wave and triangle wave. Press the button once and switch the waveform once. Press another button to change the frequency of the waveform)

基于VHDl的2FSK调制！用的是altera的quartus11软件(Based on VHDl the 2FSK modulation)

说明：  串口通信vivado实现，带有仿真文件，可实现数据收发(the uart program based on vivado)

AMBA BUS AHB/APB 的Verilog实现 包含AHB Arbiter，AHB-APB Bridge，AHB ROM Slave，AHB RAM Slave 来自g2 Microsystems Pty. Ltd.

RS（255，223）编码器，已实际运用到产品中(RS (255,223) encoder has actually applied to products)

良好的Coding Style能减少Bug，减少锁存器出现的可能以及其他隐藏逻辑错误，也有助于减小芯片面积或所用资源(Good Coding Style can reduce Bug, reduce the possibility of latches and other hidden logic errors, and also help to reduce chip area or resources used.)

嗨我是 implimanted，所有供公众使用的波特率 RatePlease 共享中测试此 codework