verilog实现的积分梳状滤波器

i2c配置SAA7113，非常有用的程序，做视频采集类必看(i2c configure SAA7113)

FPGA／CPLD技术是近年来计算机与电子技术领域的又一场革命。本书以Xilinx与Altera公司的FPGA／CPLD为主，详细介绍了FPGA／CPLD从芯片到MAX+plusⅡ、Quartus与ISE开发环境和Verilog／VHDL语言，并以交通灯逻辑控制、电子钟与点阵LED显示、LCD液晶显示及计算机ISA接口和PCI接口的设计等为例，由浅入深地详述了如何应用FPGA／CPLD进行电子设计。书中的大多数电路图和源程序已经过实例验证，读者可以直接应用于自己的设计。本书的特点是强调实用性和先进性，力求通俗易懂。 本书适用于计算机、电子、控制及信息等相关专业的在校大学生，对广大工程技术人员也具有实用价值。(FPGA/CPLD technology in recent years the field of computer technology and electronic another revolution. Book Xilinx and Altera' s FPGA/CPLD based, detailing the FPGA/CPLD from the chip to MAX+plus Ⅱ, Quartus and ISE development environment and Verilog/VHDL language and logic control traffic lights, electronic bell with dot matrix LED display , LCD liquid crystal display and computer ISA interface and PCI interface design, for example, progressive approach to detail how the application of FPGA/CPLD for electronic designs. Circuit and the source of most of the book have been instances of verification, the reader can be directly applied to their own design. Characteristic of this book is to emphasize the practical and advanced, best straightaway. This book applies to computers, electronics, control and information and other related professional college students, the majority of engineering and technical personnel also has practical value.)

CORDIC 算法可以通过不同的实现形式解决乘、除、平方根和一些三角函数运算问题。以往这些三角函数的计算问题是用硬件是 不易实现的，而CORDIC算法能够很好的解决这种问题。通过算法本身，可以将复杂的算法转换成一些很容易在硬件中实现的算法。 例如加法、移位等。该算法的基本思想是通过一系列的角度的不断偏转迭代，逐渐逼近所需的旋转角度，从而完成矢量旋转。

文件描述的是SDH 指针处理和系统同步代码 veriolg(SDH pointer processing and system synchronization code veriolg of file Description)

Material to learn how to use system verilog and how to write testbenches for verification.

vivado2017.4下的串口通信的Verilog源码，一次传输8位，包括发送模块，接受模块，顶层模块(Verilog source code for serial communication under vivado 2017.4, which transmits 8 bits at a time, including sending module, receiving module and top module)

说明：  GTH 和SMPTE IP 实现 SDI视频接收(SDI Video Receiving Based on GTH and SMPTE IP)

LDPC encoding code in 1/2code rate for DVB-T2

连续相位调制CPM信号的viterbi编解码(MSK viterbi decode)

浙江大学体系结构实验课代码 实现5级流水线带有停顿，旁路和控制竞争的处理。(Experimental Architecture, Zhejiang University course code with a pause 5-stage pipeline, bypassing the treatment and control of competition.)