登录
首页 » VHDL » which I have recently bought a CPLD Development Board VHDL source code accompani...

which I have recently bought a CPLD Development Board VHDL source code accompani...

于 2022-02-20 发布 文件大小:4.43 MB
0 361
下载积分: 2 下载次数: 1

代码说明:

这是我最近买的一套CPLD开发板VHDL源程序并附上开发板的原理图,希望对你是一个很好的帮助!其中内容为:8位优先编码器,乘法器,多路选择器,二进制转BCD码,加法器,减法器,简单状态机,四位比较器,7段数码管,i2c总线,lcd液晶显示,拨码开关,串口,蜂鸣器,矩阵键盘,跑马灯,交通灯,数字时钟.-which I have recently bought a CPLD Development Board VHDL source code accompanied the development of the plate diagram, You hope to be a good help! which states : eight priority encoder, multipliers, multi-path selectors, BCD binary switch, adder, subtraction device, the simple state machine, four comparators, seven of the digital control, i2c bus, lcd LCD allocated code switches, serial port, the buzzer sounded, matrix keyboards, Bomadeng, traffic lights, Digital Clock.

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • 用VHDL语言编写的写存储器程序,可下载在FPGA中使用
    用VHDL语言编写的写存储器程序,可下载在FPGA中使用-VHDL language used to write memory program can be downloaded in the FPGA using
    2022-06-17 11:46:31下载
    积分:1
  • 全部通过,是我的精心设计,完全满足初学者的要求。
    全部通过,是我的精心设计,完全满足初学者的要求。-all passed, I was carefully designed, fully meet the requirements of beginners.
    2022-05-29 23:49:35下载
    积分:1
  • RS232_VHDL
    FPGA控制RS232来实现串口通信,非常好的串口程序。(FPGA control RS232 serial communication to achieve very good serial procedures.)
    2020-12-28 14:49:01下载
    积分:1
  • Clifford-E.-Cummings-paper
    Clifford E. Cummings论文合集,其中关于FIFO的设计很经典(Clifford E. Cummings collection of papers, on the FIFO design classic)
    2012-07-21 01:32:34下载
    积分:1
  • described dds direct digital frequency synthesis of the basic tenets addition to...
    讲述了dds直接数字频率合成的基本原理,同时用VHDL语言编写dds原代码用于生成正弦波,并在ISE开发平台进行仿真和MATLAB验证正弦波输出结果-described dds direct digital frequency synthesis of the basic tenets addition to the use of VHDL prepared dds source used to produce sine, and ISE development platform for simulation and verification MATLAB sine wave output
    2022-07-08 20:48:31下载
    积分:1
  • LED blinker : LED1 blink every second, LED2 blink every minute
    与Xilinx spartan6评估委员会结合的小型项目示例。
    2023-02-03 21:50:03下载
    积分:1
  • fpga
    简易数字存储示波器verilog源代码 经过EP2C8Q208C8验证(Simple digital storage oscilloscope verilog source code has been verified EP2C8Q208C8)
    2013-07-16 13:04:03下载
    积分:1
  • AXI-HP-ZYNQ
    用Vivado IPI搭建的Zynq-7000 PS到PL通信过程,使用了AXI-HP接口,利用AXI-DMA IP实现直接读写DDR的过程,软件可以配置传输尺寸。(The Zynq-7000 PS to PL communication process is built by Vivado IPI. AXI-HP interface is used, and AXI-DMA IP is used to read and write DDR directly. The software can configure the transmission size.)
    2020-12-01 20:39:27下载
    积分:1
  • D-FLIP-FLOP
    ANALYSIS OF D-FLIPFLOPS
    2013-11-12 13:35:50下载
    积分:1
  • sopc_test
    在altera公司FPGA上自己构建了一个最简单的niosii sopc系统(Altera FPGA company on its own to build a simple system niosii sopc)
    2014-04-30 10:24:55下载
    积分:1
  • 696516资源总数
  • 106914会员总数
  • 0今日下载