Rotating coordinates high

acousting fingerprint enhancement

本资源包括了加法器的VHDL代码实现，供大家学习。

由verilog编写的乘法器，通过两个文件的调用实现。由于子模块的调用使得程序简化了许多。(Prepared by the Verilog multiplier, through the realization of the two documents call. As the sub-modules to simplify the procedure call makes a lot.)

ADC0809 VHDL控制程序,基于VHDL语言，实现对ADC0809控制.-ADC0809 VHDL control procedures, based on the VHDL language, to achieve control of ADC0809.

这段代码是用VHDL解释椭圆曲线密码术的。这段代码包含了使用FPGA板进行ECC加密的必要算法！ ；

altera 公司的15IP源码 亲自测试还不错 有DIV, CONTER-ALTERA the 15IP source personally tests are also good DIV, CONTER

xilink DPD V6.0 IP Core design example

关于XILINX FPGA 内部 中文培训教材-XILINX FPGA on internal training materials in Chinese

3D的效果，逼真的视觉享受，真实的场景。(3D effects, realistic visual experience, the real scene.)