Rotating coordinates high

ZBT SRAM控制器参考设计，xilinx提供，（ZBT SRAM是一种高速同步SRAM）-ZBT SRAM controller reference design for Xilinx (ZBT SRAM, a high-speed synchronous SRAM)

FPGA向SRAM中写入数据，VHDL编程-FPGA to the SRAM write data, VHDL programming

dp_xiliux 的 CPLD Verilog设计实验,7个LED演示.代码测试通过. -dp_xiliux the CPLD Verilog design experiments, 7 LED demo. code test.

程序实现自动售货机的核心功能，设有3种价格的商品，可选择数量，有找钱功能。-program vending machine at the core function, with three kinds of commodity prices, the number of choice, having to function.

针对兆瓦级风电并网逆变器主电路研制中存在的并联扩容、开关频率较低和LCL滤波器难以优化设计等问题，提出了采用交流侧串接电感再进行并联的均流方案，采用载波移相技术提高变流器的等效开关频率，提出了LCL滤波器的设计原则，并给出了上述设计的理论依据和实现方法。通过对2兆瓦风电变流器主电路的仿真验证了上述技术方案。(MW-class wind power for grid-inverter main circuit of the parallel development of existing capacity, a lower switching frequency and LCL filter design difficult to optimize the problem, a series inductor AC side in parallel are further flow program, the use of carrier phase-shifting technology to enhance the equivalent converter switching frequency, a LCL filter design principles, and gives the above-mentioned theoretical basis for the design and implementation. 2 MW of wind power converter main circuit simulation program to verify the above-mentioned technology.)

–ABCDE五路输入表示五人的选择，同意为1，不同意为0，以开关形式实现 –有半数以上同意绿灯亮，否则红灯亮。即分别对应输出Y、R为1或0 –参考仿真结果图：10ns|20ns|30ns|40ns|50ns

VHDL,简易音频数字相位表的设计与实现 数字相位测量仪在工业领域中经常用到的一般测量工具，主要应用与同频率正弦信号间的相位差的测量显示。 本系统采用FPGA实现测量的核心部分，主要由数字鉴相、累加计数器、控制器以及寄存与显示译码电路组成。该系统硬件电路简单，整个系统采用硬件描述语言VHDL作为系统内部硬件结构的描述手段，在XILINX公司的ISE9.1的软件支持下完成。可以对20Hz~20kHz频率范围内的音频信号进行采样鉴相处理，并将数据传回FPGA进行相位差计数累加、测量运算，最后送显示译码电路显示，测相范围为 ，相位测量误差 < 。 经测试结果验证，本系统充分利用FPGA对数据的高速处理能力，是系统设计高效、可靠，处理速度快，稳定性高，易于实现。 (VHDL, simple audio digital phase Table Design and Implementation of the digital phase meter general measurement tools are often used in the industrial field, the measurement of the phase difference between the main application with the same frequency sinusoidal signal. The system uses the FPGA implementation of the core part of the measurement, mainly by the digital phase, cumulative counter, the decoding circuit of the controller as well as storage and display. The system hardware circuit is simple, and the entire system using hardware description language VHDL system means a description of the internal hardware structure, completed in the XILINX company ISE9.1 software support. The audio signal in the frequency range of 20Hz ~ 20kHz sampling KAM-phase process, and the data returned FPGA retardation counted accumulation measuring operation, and finally sent to the decoding circuit, the scope of the measurement phase, the phase measurement error < . The test results verify the full u)

基本的VHDL程序本rar文件。 请点击左侧文件开始预览 ！预览只提供20%的代码片段，完整代码需下载后查看 加载中 侵权举报

AVR IP CORE 可以直接用于工程的开发和 已经通过编译和仿真-AVR IP CORE can be directly used for project development and has passed the compiler and simulation

说明：  jesd204b接收部分程序和带仿真历程(Jesd204b receiving part program and simulation process)