FPGA_verilog_DES

verilog描述的实用消抖电路，采用三个D触发器和一个JK触发器。使用emacs编写源文件，iverilog仿真通过，内有png仿真图像截屏(verilog description of the practical elimination shake circuit, using three D flip-flop and a JK flip-flop. Prepared source files using the emacs , iverilog simulation adopted, within the simulation images png screenshots)

It is vhdl code for defining a finite state machine

基于FPGA实现蜂鸣器播放音乐的功能 使用芯片为EP2C8Q208C8N,使用普通蜂鸣器，由于频率不同可实现放歌功能，本例设计的是《友谊地久天长》，使用Verilog语言编程，本例子有工程文件、仿真、波形，经过测试可以使用。(Play music based on FPGA buzzer functions using chip EP2C8Q208C8N, using ordinary buzzer, since the frequency of different functions can be realized sing, in this case the design is " Auld Lang Syne" , using Verilog language programming, this project examples files, simulation, waveform, tested can be used.)

de2-70 camera 亲测可以下载验证 直接下载使用即可

用VHDL语言写了个FLAPPY_BIRD的程序，利用板子与屏幕可以运行游戏(VHDL language to write a program FLAPPY_BIRD by the board and the screen can run the game)

NAND FLASH的控制器，Micro的样例，MCU端口有用到wishbone总线（软硬Core均可以）

用vhdl实现的booth算法乘法器，包含了multiplexer和rca adder，同时提供了一个测试文件，modelsim测试通过(Algorithm with a booth multiplier vhdl implementation, including a multiplexer and rca adder, while providing a test file, modelsim test pass)

LDPC码不同码长对比。码率选择1/2.码长分别为256，512，1024.(LDPC codes of different code length contrast. Bitrate select 1/2 yards long were 256,512,1024.)

本示例为基于FPGA红色飓风一代IDS-EP1C6/12开发板的USB传输，实现了pc端接收来自FPGA开发板的数据，并显示条纹，具体使用说明见解压后的说明文档。(This example is based on red hurricane generation FPGA development board' s USB transfer IDS-EP1C6/12 realized pc client receives the data from the FPGA development board and display stripes, detailed instructions, see the documentation after decompression.)

此代码为使用SPI 用于实现28335控制AD9959输出信号的频率、幅度(This code uses SPI The Frequency and Amplitude of AD9959 Output Signal Controlled by 28335)