-
test_utils.tar
GPIO LED 测试工具源代码,可以用来检测开发的主板GPIO LED设备是否工作正常(GPIO LED test tool source code, can be used to detect the development of motherboard GPIO LED device is working properly)
- 2012-10-23 10:20:56下载
- 积分:1
-
16位的移位寄存器,加上testbench,可以在modelsim里面运行~
16位的移位寄存器,加上testbench,可以在modelsim里面运行~-16 of the shift register and testbench, modelsim the inside running ~
- 2023-07-15 21:45:02下载
- 积分:1
-
xp2syscloclkpll
这个是讲pll的具体用法的,一般在fpga设计中都会用到 他,这个是lattice的xp2的pll的介绍,不过,fpga 都是相通的其他两家也差不多(Pll say this is the specific usage, the general design in the FPGA will use him, this is the lattice of the pll of xp2 introduction, however, fpga are connected to other two similar)
- 2007-10-31 21:03:07下载
- 积分:1
-
fir_lms
基于FPGA的自适应滤波器的实现。采用Verilog编程,2阶滤波器。(FPGA-based realization of the adaptive filter. Using Verilog programming, 2-order filter.)
- 2009-04-27 12:06:25下载
- 积分:1
-
一些有用的PicoBlaze的来源。
Some useful PicoBlaze sources.
- 2022-01-26 02:08:20下载
- 积分:1
-
generateCAcode
gps C/A码生成
生成gps32颗卫星伪码,方便,经过测试(gps C/A code generation to generate pseudo-code satellites gps32, convenient and tested)
- 2021-05-13 04:30:02下载
- 积分:1
-
SVPWM_method
给出了SVPWM算法的详细FPGA实现方法!(A detailed FPGA SVPWM algorithm to achieve the method!)
- 2017-04-05 13:43:14下载
- 积分:1
-
Verilog LDPC码
说明: LDPC码的BP译码verliong程序(BP decoding veriong program of LDPC code)
- 2020-03-03 18:14:12下载
- 积分:1
-
1、ps/2键盘输入,通过led显示ascii码
2、稍等1s可以在lcd上显示输入的字符
3、其中键盘上的backspce键是用来清屏的
4、当l...
1、ps/2键盘输入,通过led显示ascii码
2、稍等1s可以在lcd上显示输入的字符
3、其中键盘上的backspce键是用来清屏的
4、当lcd上显示满字符时,在按下按键自动清屏,从第一行显示。-1, ps/2 keyboard input, through the led display ascii code 2, wait 1s in the lcd display characters input 3, which backspce keys on the keyboard was required to settle the screen 4, when the lcd display full of characters, the press the button automatically Qing-ping, from the first line of display.
- 2022-01-31 12:27:49下载
- 积分:1
-
FFT程序,此程序虽然耗逻辑资源很大,但是在接受数据后的第7个时钟沿就可以输出FFT变换后的数据,对要求时延较低的系统可以考虑...
FFT程序,此程序虽然耗逻辑资源很大,但是在接受数据后的第7个时钟沿就可以输出FFT变换后的数据,对要求时延较低的系统可以考虑-FFT procedure, this procedure should not consume a lot of logic resources, but the data in the first seven clock can be output along the FFT transformed data, the requirements of time-delay system can be considered lower
- 2022-05-13 18:56:56下载
- 积分:1