800x600@60Hz VGA 时序产生的 Verilog

QP编程创始人所著的介绍QP编程思想的书，中文版。QP是用于嵌入式中状态机编程的开源软件。(QP programming book written by the founder of the introduction of QP programming ideas, and Chinese version. QP is open source software for embedded state machine programming.)

SDIO slave verilog code

这是fpga按键消抖的源代码，在很多fpga按键实验中都可以用到，能够进行代码移植。(This is the source code of the FPGA buttons, in many FPGA key experiments can be used, and can carry out code.)

vhdl very good debug release vhdl very good debug release

It is vhdl code for defining a finite state machine

adder 18b trong chuong trinh verilog

10_100_1000 Mbps tri-mode ethernet MAC implements a MAC controller conforming to IEEE 802.3 specification. It is designed using less than 2000 LCs/LEs to implement full function. It will use inferred PADs to reduce technology dependancies. The whole project will be finished in TEN weeks inluding verilog coding,RTL level verification. A GUI configuration interface,created by tcl/tk script language,is convenient for configuring optional modules,FiFo depth and verifcation parameters. Furthermore,a verifcation system was designed with tcl/tk user interface,by which the stimulus can be generated automatically and the output packets can be verified with CRC-32 checksum.

无线发射模块的 SRRC 成型匹配滤波设计 Verilog 代码，包含了所有测试，主模块，可以用在基带调制端，滤波器的滚降系数0.10～0.25，如果那些没有做过这方面的朋友，可以看看实现，和方法，提供一个参考和帮助

三层电梯的详细电路 Foundation版 包括强行开关门打断(Elevator control Foundation project)

拿verilog编写的som(自适应神经网络算法)，用于障碍物检测，基于FPGA可综合实验，已经在altera的cylcone上实现(Canal verilog prepared som (adaptive neural network algorithm) for obstacle detection. Based on FPGA synthesis experiments, in altera achieve the cylcone)