数字秒表的设计

10_100_1000 Mbps tri-mode ethernet MAC implements a MAC controller conforming to IEEE 802.3 specification. It is designed using less than 2000 LCs/LEs to implement full function. It will use inferred PADs to reduce technology dependancies. The whole project will be finished in TEN weeks inluding verilog coding,RTL level verification. A GUI configuration interface,created by tcl/tk script language,is convenient for configuring optional modules,FiFo depth and verifcation parameters. Furthermore,a verifcation system was designed with tcl/tk user interface,by which the stimulus can be generated automatically and the output packets can be verified with CRC-32 checksum.

it contains pdf file which has vhdl program of uart (universal asynchoronus receiver and transmitter). which very simple and easy to understand

基于FPGA微分程序代码及其电路驱动程序(Based on FPGA differential program )

USB Blaster full production data

介绍 verilog 语言，用于实现包括乘法计算两个 32 位数字。在码，我输入我的 CWID 和 41411 来验证功能。您可以更改要计算不同的值的十六进制文件。体系结构 ︰ 携带-波纹 + 进位跳跃。

本程序是fpga控制flash的读写程序，包括了程序和仿真时的测试文件(fpga flash)

说明：  基于quartusII的QDPSK调制解调vhdl程序。(Modulation and demodulation based quartusII of QDPSK vhdl program.)

说明：  用verilog编写的ddr3芯片读写控制程序，经过调试的，可以直接拷贝。已在Xilinx Spartan6 FPGA调试验证。(The ddr3 chip read-write control program written in verilog can be copied directly after debugging. Tested and verified on Xilinx Spartan6 FPGA.)

说明：  这是一个带声音的弹球小游戏，通过VGA口显示，通过扩展口JA的 pin4和 pin GND输出声音， BTN3 BTN2 控制挡板左右移动，弹球和挡板都自带动画效果(This is a band sound pinball game, through the VGA port shows that through the expansion of the mouth of the JA and pin4 output pin GND voice, BTN3 BTN2 control baffle around Mobile, pinball and baffle all bring their own animation effects)

用FPGA分频，做一个有时分秒的时钟，并用数码管显示(FPGA divide a sometimes every minute clock, and digital display)