-
CPU-Verilog
说明: 简单流水线CPU,使用 verilog实现,实现一条指令的整个流程(Implementation of Simple Pipeline CPU Verilog)
- 2020-06-23 19:40:01下载
- 积分:1
-
cfft_control
vhdl code for cyclic cfft control
- 2011-04-05 14:42:09下载
- 积分:1
-
基于SOPC EP2C5开发板的I2C总线的A/D D/A例程
基于SOPC EP2C5开发板的I2C总线的A/D D/A例程-A/D AND D/A routings interfaced with i2c based on sopc ep2c5
- 2022-01-25 22:27:04下载
- 积分:1
-
UDP / IP上的Spartan3E以太网通信
UDP / IP上的Spartan3E以太网通信通过斯巴达3E发送UDP数据包到/从我的电脑。
- 2022-06-20 12:49:08下载
- 积分:1
-
FPGA SDRAM with the operation of the specific see internal note
用FPGA实现SDRAM的操作,具体操作见内部说明文件-FPGA SDRAM with the operation of the specific see internal note
- 2022-01-22 01:54:54下载
- 积分:1
-
等精度频率计
基于FPGA的等精度频率计,包括工程,doc和一些查找资料(An equal precision frequency meter based on FPGA, including engineering, Doc, and some lookup data)
- 2020-10-30 21:39:57下载
- 积分:1
-
一个8X8的矩阵键盘的VHDL文件,并且有长安键和短按键之分,即一共能做到128个键值,扫描用的时钟用1ms的就行了...
一个8X8的矩阵键盘的VHDL文件,并且有长安键和短按键之分,即一共能做到128个键值,扫描用的时钟用1ms的就行了-A 8x8 matrix keyboard VHDL files and have Changan and short keys of key points, namely, to achieve a total of 128 keys, scanning with the clock used on the list of 1ms
- 2022-08-14 17:54:21下载
- 积分:1
-
nco11000
实现输入一正弦波和噪声的叠加,介绍详细欢迎下载(The input of a superposition of sine wave and noise introduced in detail)
- 2010-05-16 14:19:53下载
- 积分:1
-
TFT_CTRL_800_480_16bit
文件用于驱动TFT屏,分辨率800*400,平台为quartus13,芯片为cycloneIV(The file is used to drive the TFT screen with a resolution of 800*400. The platform is quartus 13 and the chip is cyclone IV.)
- 2019-04-12 09:22:29下载
- 积分:1
-
manchester_verilog
manchester_verilog源代码(manchester_verilog source code)
- 2008-07-11 08:50:53下载
- 积分:1