硬件设计vhdl_cpu1，1。您可以复制和分发该副本…

RFID防碰撞算法的研究，以及对其各种算法的仿真，以及改进算法的仿真和比较。(RFID anti-collision algorithm, as well as its simulation algorithms, and improved simulation and comparison algorithms.)

cpld/fpga常用加法器设计的verilog程序-cpld/fpga common adder Verilog design procedures

用VHDL硬件语言实现的iic顶层控制程序-Using VHDL hardware language to achieve the top level of the IIC control procedures

Learning Verilog Chinese Version Part 8

8级cordic 算法verilog (8 cordic algorithm verilog)

说明：  彩色TFT液晶显示控制电路设计及其ASIC实现(TFT color LCD control circuit design and ASIC realization)

用VHDL编写的8259控制,供大家使用.-with VHDL control of the preparation of the 8259, for your use.

Blessing_3_v3_9_6稳定盈利set，仅限AUDNZD货币对，周期M1。 使用本压缩包内的SET，LAF默认是15，根据历史测试来看具有较大的风险，需要手动规避数据。 合理设置为LAF=8，请自行设置和调试，找到自己合适的风险值。 (Blessing_3_v3_9_6 stable profit set, only AUDNZD currency pairs, cycle M1. Use this package in the SET, the default is 15 fans, according to the angles of history test has great risk, need to avoid data manually. Reasonable set to fans = 8, please make your own setting and debugging, find their proper risk value.)

基于DE2开发板的VGA显示模块，仅供大家参考(DE2 development board based on the VGA display module, for your reference)

VHDL基本运算，采用8位为乘法器，将两个8位字符串的值输入相乘后