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vhdl classic example
vhdl经典实例――信号灯控制,入门者必须掌握-vhdl classic example-- to control lights, beginners must master
- 2022-06-02 01:52:15下载
- 积分:1
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介绍了光纤光栅感温火灾探测系统的应用原
理,并重点阐述了用CPLD 设计虚拟MC14499 器件模
块,给出并解释了用Verilog HDL 语言实现的...
介绍了光纤光栅感温火灾探测系统的应用原
理,并重点阐述了用CPLD 设计虚拟MC14499 器件模
块,给出并解释了用Verilog HDL 语言实现的部分程
序和仿真测试结果。-Introduction of Fiber Bragg Grating temperature fire detection system principles, and focuses on the use of CPLD design virtual MC14499 device module, are given and explained using the Verilog HDL language to achieve some of the procedures and simulation test results.
- 2022-03-01 16:23:41下载
- 积分:1
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112
用MSP430进行压力测试,完成数据的分析(with msp430 to continue on press test.to complete about the anlysys about data)
- 2012-08-31 16:10:15下载
- 积分:1
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m73a_nand_model
说明: Micron公司m73a系列nand flash仿真模型及测试文件(micron m73a series nand flash simulation model and testbench)
- 2011-03-25 22:17:32下载
- 积分:1
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DE2_SD_Card_Audio
FPGA开发,DE2开发板上实现,从SD卡读出MP3文件并播放,(即是开发一个简单的MP3播放器)(FPGA development, DE2 development board realize, from the SD card to read out and play MP3 files, (that is, the development of a simple MP3 player))
- 2020-11-28 21:49:28下载
- 积分:1
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This project features a full
This project features a full-hardware sound compressor using the well known algorithm: IMA ADPCM.
The core acts as a slave WISHBONE device.
The output is perfectly compatible with any sound player with the IMA ADPCM codec (included by default in every Windows). Includes a testbench that takes an uncompressed PCM 16 bits Mono WAV file and outputs an IMA ADPCM compressed WAV file.
Compression ratio is fixed for IMA-ADPCM, being 4:1.
PLEASE NOTICE THAT THIS CORE IS LICENSED UNDER http://creativecommons.org/licenses/by-nc-sa/3.0/ (Creative Commons Attribution-Noncommercial-Share Alike 3.0 Unported). That means you may use it only for NON-COMMERCIAL purposes.
- 2022-07-25 20:05:07下载
- 积分:1
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sos_module
用FPGA实现sos摩尔密码,即输出电平信号短长短。就是有次序的控制输出莫斯密码的“点”,“画”和“间隔”。而 control_module.v 是一个简单的定时触发器,每一段时间都会使能sos_module.v。(Realized by FPGA sos mole password, the output signal level of short duration. There is a sequence of output control points Moss password, painting and intervals. And control_module.v is a simple timer triggers, each period of time will enable sos_module.v.)
- 2016-09-20 16:26:29下载
- 积分:1
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all passed, I was carefully designed, fully meet the requirements of beginners....
全部通过,是我的精心设计,完全满足初学者的要求。0-99自动记数-all passed, I was carefully designed, fully meet the requirements of beginners. 0-99 automatic counting
- 2022-05-05 06:11:20下载
- 积分:1
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qam_64
Verilog语言下QAM调制的DDS实现(The QAM Modulation DDS achieve)
- 2021-02-20 11:59:43下载
- 积分:1
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Verilog数字系统设计教程(第二版) 夏宇闻
Verilog数字系统设计教程(第二版) 夏宇闻(Verilog Digital System Design Course (2nd Edition) Xia Yuwen)
- 2020-06-20 18:40:02下载
- 积分:1