altera de2 开发板 vga lcd控制quatus 工程

基于Verilog的图像采集、处理和存储程序，初学者参考，高手绕道。(Verilog-based image acquisition, processing and storage procedures, beginners reference, master bypass.)

说明：  ZEDBOARD的管脚分配图和约束文件，包括PCB图和xdc文件(Pin assignment of ZEDBOARD)

硬件描述语言相关芯片程序源码Chip hardware description language-related program source code(Chip hardware description language-related program source Chip hardware description language-related program source code)

VGA彩条信号显示控制电路设计,能通过vga显示横条纹竖条纹棋盘条纹(VGA color signal display control circuit design)

用VHDL实现一个四位十进制计数器来进行计数，并且仿真通过-To use VHDL to achieve a 4 decimal counter to count, and the simulation through the

交通灯控制（VHDL）-Traffic Light Control (VHDL)! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! !

OFDM_TX_CR802.11-master 802.11协议 ofdm开发(OFDM_TX_CR802.11-master)

16位高速数字相关器的VERIOLOG程序，已经编译通过了，可以使用(16-bit high-speed digital correlator VERIOLOG program has been compiled by, you can use)

fft变换三个中的一个（站长：三个代码算一个）-one of the three fft transfermation code

采用FPGA实现的DDS波形发生器源码，可以实现频率幅值变换、正弦波、方波、三角波输出，输出频率可达1MHz(FPGA implementation of the DDS waveform generator source frequency amplitude transform, sine wave, square wave, triangle wave output, the output frequency up to 1MHz)