altera de2 开发板 vga lcd控制quatus 工程

Xapp 200 64 bit DDR SDRAM design files for Xilinx Vertix

verilog实现的“并行输入、并行输出移位寄存器”-verilog to achieve a " parallel input, parallel output shift register"

波形发生器，用于编写testbentch文件。非常实用-Waveform generator, for the preparation of testbentch files. Useful

VHDL语言基本数学运算库-VHDL basic arithmetic library

FM接收机 基于FPGA的调频收音机的设计 用VEIRLOG语言编程，利用QUARTUSii与MODELSIM联合仿真(FM receiver on FPGA FM receiver design With VEIRLOG language program, use QUARTUSii and MODELSIM joint simulation)

说明：  Verilog 黄金参考指南是 Verilog 硬件描述语言及其语法 语义 合并以及将它应用到硬件设计的一个简明的快速参考指南。(Verilog Golden Reference Guide is a concise and fast reference guide for Verilog Hardware Description Language and its syntax and semantics merging and its application to hardware design.)

vhdl编程语言电子书，英文的，有很多例子(VHDL programming language e-books, in English, there are many examples of)

说明：  通过MATLAB产生单脉冲信号的数据，存储下来作为verilog代码实现的DDS的数据源，用于验证DA数据的ddio的调试是否有问题。(The data of monopulse signal generated by MATLAB is stored as the data source of DDS implemented by Verilog code to verify whether the ddio debugging of DA data is problematic.)

manchester_verilog源代码(manchester_verilog source code)

对视频编解码芯片ADV7181进行合理的配置，使其输出符合ITUR656标准的视频流-Of the ADV7181 video decoder chip for a reasonable configuration, so that the output in line with the standard video streaming ITUR656