针对于Virtex5FPGA的DDR2读写测试的完整工程

UML2 apprendre a modeliser a l aide de UML

ofdm的发射链路和接收链路的Verilog源代码，包括长短训练序列的生成，导频插入，加cp，ifft。(Source code of transmission link and reception link of OFDM)

Srikanth Vijayaraghavan - A Practical Guide for SystemVerilog Assertions-Srikanth Vijayaraghavan- A Practical Guide for SystemVerilog Assertions

uart documentation, july 17, 2019. the document describes the basics of verilog programming and how to implement them on an fpga device

这是一个基于可编程逻辑器件的程序，用来实现自动转换量程频率计控制器，该程序在可以再仿真器上仿真实现-This is a programmable logic device based on the procedures used to automatically convert the frequency range of the controller, the program can be in the simulation simulator

基于网口的收发数据及解析数据内容的verilog代码实现(Based on the Internet port to send and receive data and parse the contents of the data verilog code)

FPGA时序分析说明。对于高速时钟设计中的时序分析与约束有帮助(FPGA,TIME)

A programming language that can decode alpha numeric

多功能数字钟，在quartusII软件平台上实现的verilog源代码。大家试试看。(Multifunctional digital clock in quartusII software platform to achieve the verilog source code. We try.)

一种半加器的算法，是基于VHDL软件仿真。请大家下载参考！-A full-adder algorithm is based on the VHDL software emulation. Please download the reference!