简易报文识别器

说明：  8位大小比较器的VHDL源代码，Magnitude Comparator VHDL description of a 4-bit magnitude comparator with expansion inputs(eight compared with the size of the VHDL source code, Magnitude Comparator VHDL description of a 4-bit magnitude comparator inputs with expansion)

NN CONTROLLER FOR UPQC

9针的rs232与fpga之间的串口通信源程序(Rs232 9 pin serial communication with the source between fpga)

给大家上传一本非常好的关于verilog-hdl的电子书，实用，易懂，易学。此为第七章(Give us a very good upload on verilog-hdl of e-books, practical, easy-to-understand, easy to learn. This is the Chapter VII)

AD706在Sparten6使用的FPGA代码，测试通过(AD706 FPGA Code In Sparten6)

ICA (Principal Component Analysis) algorithm and procedures, GSM is GMSK modulation signal generation, On neural network control.

运用quatusii工具基于verilog实现匹配滤波器

ARM处理器的IP核，用verilog编写的，对处理器和相关的CPU架构知识有很大帮助。(ARM processor IP core, written in verilog processor and CPU architecture knowledge.)

数字化，宽带化，是当今无线通信的重点主流方向，FPGA以其功能强大，开发周期短，投资少，可重复修改，开发工具智能及软件可升级等特点成为无线通信首选。(Digital, broadband, is the focus of today s mainstream wireless communications, FPGA with its powerful, short development cycle, low investment, repeatable modify, intelligence and software development tools and other characteristics can be upgraded to become the first choice of wireless communication.)

这是用于阵列乘法器baugh wooley 。这是写Verilog代码。它表明8位阵列乘法。这是输入含有8,8每输出有15位