verilog2000更新部分，请对照前一个标准。加入了一些新的支持

VIVADO dma以及vdma 使用文档 基于ZYNQ 7020(vivado DMA&VDMA example text of zynq)

1、ps/2键盘输入，通过led显示ascii码 2、稍等1s可以在lcd上显示输入的字符 3、其中键盘上的backspce键是用来清屏的 4、当lcd上显示满字符时，在按下按键自动清屏，从第一行显示。-1, ps/2 keyboard input, through the led display ascii code 2, wait 1s in the lcd display characters input 3, which backspce keys on the keyboard was required to settle the screen 4, when the lcd display full of characters, the press the button automatically Qing-ping, from the first line of display.

vhdl very good debug release vhdl very good debug release

增强型8051的VHDL源代码，两个周期执行一条指令，仿真工具为Modelsim，开发板为Altera的EP1C20开发板-enhanced 8051 VHDL source code, the implementation of a two-cycle instruction, simulation tools for Modelsim, development board for the Altera EP1C20 development board

dsp和fpag通信的测试程序，包含整个工程和signaltap测试信号。(the the dsp and fpag communications test procedures, including the entire the engineering and signaltap test signal.)

基于vhdl可用的数字频率计，误差较小，精准度较高。文件中还包含了与arm的通信模块、

完成一个1位全减器的设计。以全减器为元件程序完成8位减法器设计。(Completed a one minus the whole design. Full reduction is to complete eight subtraction element program design.)

Convolotional Decoding Based on Viterbi Algorithm

说明：  这是一个关于OQPSK的Matlab程序 这是一个关于OQPSK的Matlab程序 (This is a OQPSK the Matlab program is a program of OQPSK in Matlab)

说明：  多摩川绝对值编码器的NRG协议源代码,我们公司用的，我修改的解码程序(Tamagawa NRG absolute encoder protocol source code, used by our company, I modified decoding process)