verilog2000更新部分，请对照前一个标准。加入了一些新的支持

说明：  VC707_MIG_DDR3.sim文件夹中是仿真的文件：testbench和DDR3模型参数 VC707_MIG_DDR3.srcs文件夹中是源文件，包含DDR3的控制、收发模块、顶层文件(VC707_ MIG_ In ddr3.sim folder are simulation files: testbench and DDR3 model parameters VC707_ MIG_ Ddr3.srcs folder is the source file, including DDR3 control, transceiver module, top-level file)

Xilinx fpga 设计培训中文教程,比较好的学习FPGA入门的教程(Xilinx fpga design training for Chinese curricula, better start learning FPGA Tutorial)

说明：  sd卡的verilog代码，包含一些sd卡例程(SD card Verilog code, including some SD card routines)

说明：  VHDL BISS,SSI,ENDAT2.2, ENCODER

FPGA AD数据采集模块，实现模拟信号到数字信号转换。(FPGA AD data acquisition module, the analog signal to digital signal conversion.)

基于FPGA的交通灯的设计 有Verilog HDL 源码、仿真图与引脚配置图，已下载实现 -FPGA-based design of traffic lights have Verilog HDL source code, simulation map with pin configuration map has been downloaded realize

CH2CH1VHDL 数字电路参考书所有程序4-CH2CH1VHDL digital circuit reference all proceedings 4

NIOS II IDE 编程， LCD测试程序，仅供参考。-NIOS II programming IDE, LCD testing procedures, for information purposes only.

用MSP430进行压力测试，完成数据的分析(with msp430 to continue on press test.to complete about the anlysys about data)

4. If a modified source code is distributed, the original unmodified -- source code must also be included (or a link to the Free IP web -- site). In the modified source code there must be clear -- identification of the modified version.-4. If a modified source code is distributed, the original unmodified-- source code must also be included (or a link to the Free IP web-- site). In the modified source code there must be clear-- identification of the modified version.