verilog2000更新部分，请对照前一个标准。加入了一些新的支持

说明：  there's a clock divider for DE2 altra board clock (50MHz)

通过VERILOG编写的AD9516时钟芯片SPI配置代码(CONGIGURE THE ad9516)

说明：  难得的soc设计用的ddr3 verilog，可用于学习！！！！！有datasheet ，可仿真(soc ddr3 verilog for study !!)

这个程序是为了区分SIGNAL和VARIABLE在不同情况下要怎样使用的例程，程序中使用了三种情况来说明问题(This program is designed to differentiate between routine SIGNAL VARIABLE in different situations and how you want to use, the program uses the three cases to illustrate the problem )

VHDL的初学者可以参考此VHDL加法器，相信会给你带来不小的收获-VHDL beginner can refer to the VHDL adder, I believe will bring you not a small harvest

CPLD对mcbsp的收发操作，占用资源很少(CPLD to mcbsp transceiver operation, small footprint)

通过监测工作状态实现带有IIC通讯功能的数据发送接收(to implement the sending and receiving data function of iic communication )

Altera官网上关于SOPC中自定义组件（PWM）的实例，官网上现在没了。。可很多书上都在用-Altera in the official line on the SOPC custom component (PWM) of the examples are not the official line. . Can be a lot of books are in use. . .

基于FPGA的视频图像加密系统 DE2_70+TRDB—D5M+VGA(FPGA-based video encryption system DE2_70+TRDB-D5M+VGA)

一些较为经典的VHDL代码,专注于信号分析与检测方面-Some of the more classic of the VHDL code, focusing on signal analysis and testing