verilog2000更新部分，请对照前一个标准。加入了一些新的支持

说明：  Convolutional neural network code for fpga

A latch3 written in VHDL.

使用verilog语言，滚动显示“verilog”字符串程序代码及相关说明(Using verilog language, scrolling display " verilog" string code and instructions)

说明：  Use of Kalman and EKF on two-phase permanent magnet synchronous motor of the state estimate CDCDCDCDCCC

report for a report for a class

说明：  图像采集 VGA输出 图像的边缘 ov7670(V image acquisition VGA output image edge)

用AHDL语言编写,MAXPULS开发.通信不受外部时钟速率和数据字节数目限制.-with AHDL prepared MAXPULS development. Communications from external clock rate and restriction on the number of data bytes.

开发板原理图 自己可以设计开发板为什么一定要买呢(Development board schematic can design their own development board why they must buy it)

NIOS II IDE 编程， uart_txd测试程序，仅供参考。-NIOS II IDE programming, uart_txd testing procedures, for information purposes only.

2FSK的matlab仿真，叠加了高斯白噪声(2FSK matlab simulation, superimposed on a Gaussian white noise)