VHDL与源代码包

说明：  潘松那本书上用vhdl语言描述的16位并入并处加法器(Pan book vhdl language used to describe the 16-bit adder into his)

基于FPGA的数字电压表 两种方案 一种VHDL一种Verilog(Digital voltmeter based on FPGA)

build a tv box on fpga cyclone 2

FFT快速傅立叶变换-verilog，基于verilog的FFT源码，QuartusII上仿真通过(FFT Fast Fourier Transform-verilog, the FFT-based verilog source, QuartusII through the simulation)

说明：  这是本人曾经参与的一个DDR controller接口项目，主要是FPGA rtl实现，仅供参考。(This is a DDR controller interface project that I once participated in, mainly implemented by FPGA RTL, for reference only.)

采用verilog实现的有限域GF(28)弱对偶基乘法器，本原多项式: p(x) = x^8 + x^4 + x^3 + x^2 + 1 ，多项式基: {1, a^1, a^2, a^3, a^4, a^5, a^6, a^7}，弱对偶基: {1+a^2, a^1, 1, a^7, a^6, a^5, a^4, a^3+a^7}(Verilog achieved using the finite field GF (28) weak dual basis multiplier)

是一个用vhdl语言编写的pwm程序，可以方便地用来和nios连接，实现对nios的功能扩展。-is a VHDL language with the PWM procedures can be used to facilitate connections and nios, nios to achieve a functional extension.

fpga debounce filter code in vhdl

一个关于跨越异步时钟边界传输数据的解决方案(The solution of transfering data across asynchronous clock boundary.)

传感信号无线数字传输系统的设计与实现.kdh(err)