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can-lite-vhdl-master
CAN VHDL Code. Behavioral implementation of CAN bus interface.
- 2021-01-19 21:48:41下载
- 积分:1
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DDS
可以产生正弦波,三角波、锯齿波、方波,要求频率1Hz-100kHz,步进1Hz,具有自动扫频功能;
正弦波的相位可调,方波的占空比可调;
(Can generate sine wave, triangle wave, sawtooth wave and square wave, the required frequency of 1 hz- 100 KHZ, step 1 hz, with functions of automatic frequency sweep
The phase adjustable sine wave, square wave duty ratio is adjustable )
- 2021-05-07 02:58:36下载
- 积分:1
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ytupn
Very suitable for the study using computer vision, Analysis of the signal time domain, frequency domain, cepstrum, cyclic spectrum, etc. The performance of the program has reached a high level.
- 2017-09-02 18:07:13下载
- 积分:1
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calculator_final
清华大学电子课程设计:Verilog,QuartusII可正确运行,可下载到FPGA上,音乐计算器,完成两个三位数的运算,有注释,很强大!!(Verilog, QuartusII run correctly, can be downloaded to the FPGA, music, calculator, completed two three-digit operations, there are notes, very powerful! !)
- 2020-08-16 23:38:25下载
- 积分:1
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NAND_flash_verilog_vhdl
很好的NAND Flash 硬件驱动语言,支持VHDL和verilog 语言方便移植,如果有想用FPGA直接驱动NAND flash而又不知如何下手的朋友肯定喜欢。(NAND Flash Controller Reference
This reference design is used to interface a NAND Flash device and provides a simple host end interface. The host
end interface of this design is user-configurable. It provides buffer select signal, buffer write enable signal, address
bus, data bus, error status signal, control and handshake signals for the user......)
- 2021-03-08 22:59:28下载
- 积分:1
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test_ad9852
使用FPGA来控制DDS信号的产生,从而达到高频信号产生的目的。使用的DDS芯片为AD9852,在QuartusII下编写。(Using the FPGA to control the DDS signal generation, so as to achieve high-frequency signal generation purposes. Use of DDS chip AD9852, in the QuartusII prepared.)
- 2010-01-27 17:02:16下载
- 积分:1
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ethernet_tri_mode_rtl.tar
以太网控制器verilog,含有mac,mii接口(Ethernet controller verilog, containing mac, mii interface)
- 2007-12-19 23:51:08下载
- 积分:1
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Serial_Adder
注意:是verilog语言写的
一bit的全加器,实现4位数的串行加法器,一个时钟能完成一次一bit的全加(Note: It is verilog language to write a bit full adder, to achieve four-digit serial adder, a clock can be completed once a bit full adder)
- 2020-10-30 20:09:55下载
- 积分:1
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FPGA_emif
接口模块,通过对高位地址的编码可实现在一个FPGA中配置四个独立的功能模块,每个功能模块具有一个带FIFO的输出口和13个独立的可由DSP读写的寄存器,寄存器功能可自定义。模块还包含两个全局寄存器,可实现全局复位,中断等功能。该模块以应用于实际的项目中,目前运行良好(FPGA to emif)
- 2020-12-04 10:59:26下载
- 积分:1
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ba_ker
巴克码装到信息内同时将巴克码识别出来,实现帧同步的VHDL设计(Barker code loaded to the information identified while Barker code, VHDL design to achieve frame synchronization)
- 2014-05-18 17:37:39下载
- 积分:1