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RGMII测试程序
RGMII测试程序,在板子测试验证过,可以使用,初学者可以参考下
- 2022-03-19 00:31:59下载
- 积分:1
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加法器和乘数
不同类型的加法器和乘法器在 verilog 中实现。这些都是: 携带看加法器,carryskip 加法器,booth 型乘法器,阵列乘法器
- 2022-05-20 12:07:35下载
- 积分:1
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atomicops_internals_mips_gcc
Protocol Buffers - Google s data interchange format.
- 2015-10-07 09:49:45下载
- 积分:1
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coubter_key
ISE环境下Verilog编程实现机械按键去抖(ISE Verilog programming environment under mechanical debounces)
- 2015-12-13 12:52:42下载
- 积分:1
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ex4
statemachine project for my school
- 2011-12-02 21:07:27下载
- 积分:1
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FPGA-OFDM-communication-system
说明: 基于ofdm系统的各个模块的VHDL程序,软件是用的ISE仿真的。绝对有用。(Ofdm systems based on VHDL program of each module, the software is to use the ISE simulation. Absolutely useful.)
- 2011-03-18 16:58:35下载
- 积分:1
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基于FPGA和matlab的IIR滤波器设计
基于FPGA和matlab设计的IIR滤波器,利用matlab的simulink工具进行设计,包含了源码和相关文档说明,希望能够对大家有所帮助
- 2022-04-02 06:35:36下载
- 积分:1
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fre
本设计是基于EP4CE15F17C8N和12864液晶的频率计程序(The design is based EP4CE15F17C8N and 12864 LCD frequency meter program)
- 2015-08-12 08:39:32下载
- 积分:1
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snake
贪吃蛇程序,用verilog实现,可以运行只要修改一下相应的FPGA芯片类型和VGA接口相应的引脚(Snake program, using Verilog to achieve, you can run as long as the appropriate to modify the corresponding FPGA chip type and VGA interface to the corresponding pin)
- 2016-01-16 21:11:14下载
- 积分:1
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chuankou
本实验为UART回环实例,实验程序分为顶层unrt_top、发送模块uart_tx、接收模块 uart_rx,以及时钟产生模块clk_div。uart_rx将收到的包解析出8位的数据,再传送给 uart_tx发出,形成回环。参考时钟频率为100MHz,波特率设定为9600bps。(This experiment is an example of UART loop. The experimental program is divided into top-level unrt_top, sending module uart_tx, receiving module uart_rx, and clock generation module clk_div. Uart_rx parses the received packet into 8 bits of data and sends it to uart_tx to send out, forming a loop. The reference clock frequency is 100 MHz and the baud rate is set to 9600 bps. stay)
- 2020-06-24 01:40:02下载
- 积分:1