一种学习用的小程序，主要用与VHDL仿真的全加器的一段代码！大家可以下载进行修改于仿写...

基于FPGA的JPEG图像压压缩，实现JPEG图像的实时压缩 (Real-time compression pressure compressed FPGA-based JPEG images, JPEG images)

TCD1209D驱动程序 Verilog语言(TCD1209D driver Verilog language)

能够成功的实现走马灯功能，使LED循环亮灭(To succeed the implementation of the version function, make the LED circular light out)

基于sopc ep2c5开发板的液晶字符显示例程-Sopc ep2c5 development board based on liquid crystal character display routine

EDA中常用模块VHDL程序，不同时基的计数器由同一个外部是中输入时必备的分频函数。分频器FENPIN1/2/3(50分频=1HZ，25分频=2HZ，10分频=5HZ。稍微改变程序即可实现)-EDA VHDL modules commonly used procedure, the time- with a counter by the external input is required when the sub-frequency functions. Frequency Divider FENPIN1/2/3 (50 1HZ frequency = 25 = 2HZ-frequency, frequency = 10 points Stripper. A slight change in procedure can be realized)

经典的OV5642的verilog驱动程序(Verilog Driver of Classic OV5642)

通过PC串口调试助手向MINI板发数据（HEX），在数码管显示接收到的数据，并回传给PC(The debugging assistant sends data (HEX) to MINI board through PC serial port, displays the received data in the digital tube and sends it back to PC)

SMbus通讯协议的Verilog程序段，已通过Moldesim的仿真，可用(Verilog program segment of the SMbus communication protocol, has been through the Moldesim simulation, the available)

用于视频图像编码的8×8DCT变换，可用于MPEG4.H263等VHDL编程-For video images encoded 8 × 8DCT transform, can be used to MPEG4.H263 such as VHDL Programming

数字钟(Digital clock)