FPU Floating point unit verilog

用VHDL实现60秒倒计时的功能 倒计时为0时蜂鸣器持续响起(Continued sounded to achieve 60 seconds of the countdown function with VHDL countdown to the 0:00 buzzer)

能产生正弦波、三角波、方波和e指数衰减的扫频波，且相关参数可调(Can produce sine wave, triangle wave, square wave, and e exponential decay wave sweep and adjustable parameters)

单周期16位CPU的设计,我们的计算机组成原理课设，可以实现R型、I型和J型指令，内有报告和指导书(Single-cycle 16-bit CPU design, our Principles of Computer Organization class set, you can achieve R-type, type I, and J-type instructions, reports and instructions)

应用背景此組程式代碼可應用在Quartus II verilog VHDL編寫LCD模組 且可在DE2模擬版上進行實驗操作!!关键技术此程式碼 可幫助初學者應用在LCD顯示器 上顯示FPGA的文字 再進行適當的修改可以應用在自己的地方!!

说明：  这个是64bit矩阵乘法实现代码，语言是verilog。(This is the 64 bit matrix multiplication implementation code, and the language is Verilog.)

自动售货机，根据所要的东西，自动收费，并进行找零(Vending machine, according to what you want to automatically charge and conduct Keep the change)

fpga 设计全攻略，很好的fpga入门提高资料(the fpga design Raiders, good fpga the Getting Started improve data)

FPGA数字图像处理实现均值滤波，并且仿真将生成图片写出TXT格式以便使用MATLAB查看(Mean filter is realized by digital image processing in FPGA, and the generated image is written in TXT format for viewing with MATLAB.)

STT-MRAM磁性存储器全部verilog代码和仿真验证代码，包括行为模块，读写模块和控制模块，已经经过验证完全正确(STT-MRAM magnetic memory all the code and simulation code, including behavior module, reader module and the control module, has been proven entirely correct)

Xapp 200 64 bit DDR SDRAM design files for Xilinx Vertix