crc循环冗余校验码，用于对传输信号进行编码校验，是信息更可靠...

MODELSIM开发的模拟CPU，用VHDL语言描述，采用累加结构-ModelSim simulation developed CPU, using VHDL language description of the structure of the use of cumulative

电梯的vhdl设计，6层楼含开关门，警报，内部请求，外部请求-Vhdl elevator design, six floors with switch doors, alarm, internal requests and external requests

四位拨妞开关作为输入，当输入值变化时将其转化成两位输出(The four DIP Niu switch as an input, when the input value changes, be converted into two output)

这个我也太清楚是什么 反正师兄们说有用 发大家-I am also very clear that what is useful anyway, say senior U.S. fa

uart 收发器 verilog 代码，实现自收发功能 sys clk = 25m, baud 9600 停止位1， 无校验位； 代码实现了串口自收发功能，及把从 PC 收到的内容都发送会 PC, 其他波特率，自行修改代码即可，在 alter 的FPGA 上调试通过； (verilog code uart transceiver to achieve self-transceiver function sys clk = 25m, baud 9600 1 stop bit, no parity code from the transceiver features a serial port, and the contents received from the PC will send the PC, another Potter rate, self-modifying code can, in the alter of the FPGA, debugging through )

可以用于按键去抖动的电路应用，采用vhdl编写-Button can be used to jitter circuit applications, the preparation of the use of VHDL

说明：  基于CycloneV FPGA与电阻网络的数模转换器代码，能够实现键控更改频率，通过ROM IP核存储波形数据。(Digital to analog converter code based on cyclonev FPGA and resistance network can realize keying change frequency and store waveform data through ROM IP core.)

页面置换算法中的三种算法相关程序代码 FIFO LUR OPT-yemianzhihuansuanfa

ALTERA FPGA CLPD

VHDL汇编语言原理及源代码。spartan 3e开发板试用。(VHDL language.)