crc循环冗余校验码，用于对传输信号进行编码校验，是信息更可靠...

说明：  编码方式为213的Viterbi卷积码编码器和译码器的FPGA的实现，包含整个QuartusＩＩ的工程文件，解码方式为寄存器交换法(Encoding for the 213 convolutional code encoder and Viterbi decoder FPGA realization of the project file that contains the entire QuartusII, decoding method for the register exchange)

8051IP 核源代码（VHDL）.RAR-8051IP nuclear source code (VHDL). RAR

sm4 VERILOG 代码实现及其在无线网络3G中的应用(sm4 VERILOG)

超低速的光纤一体发接收发送器,同于以前的光纤一体化接头都只适用于2M以上的通讯,如需将232等低速信号用光纤传输出,需要加复杂的调制解调电路,网动光电新生产的这款光纤头主要针对低速信号,可以传送DC-500KPS的信号,极大地简化了硬件设计.(Ultra-low-fat whole-speed fiber-optic transmitter receiver with fiber-optic integration in the previous joint only applies to more than 2M communications, etc. For the 232 low-speed optical fiber transmission of signals, the need to increase the complexity of the modulation and demodulation circuit, the net move Photoelectric new production of this first major response to low-speed fiber-optic signal, DC-500KPS can send the signal, greatly simplifying the hardware design.)

说明：  很好的免费学些 verilog教程 欢迎下载(Learn a good free download verilog tutorials welcome)

rc6 algorithm designed based on verilog and is verified

用NiosII实现的数字钟，经过本人测试运行正常，开发环境：QuartusII6.0和NiosII IDE6.0-NiosII achieved with digital clock, after I run the normal tests, development environment: QuartusII6.0 and NiosII IDE6.0

32-bit shifter, shifter, 32-bit.Very goog as a study file.

USB3.0开发板资料，采用CYUSB3.0(USB3.0 development board, using CYUSB3.0)

设计了一个电子时钟，功能包括定点报时，设置闹钟，校时等(Designed an electronic clock, features include fixed-point timekeeping, setting alarms, school hours, etc.)